By Calista Redmond, CEO, RISC-V International
RISC-V has rapidly emerged as the leading standard Instruction Set Architecture (ISA) in the world of processor design and implementation. Unlike proprietary architectures, RISC-V is a standard that is open to anyone to build processor designs with, offering unprecedented opportunities for innovation. The significance of RISC-V, its impact on the tech industry, and the role of RISC-V International in fostering growth and development in this space span the full breadth of computing from small, lightweight processors to robust, high-performance processors. RISC-V continues to build market share from deep investment by multinational corporations to VCs partnering with start-ups, and from university classrooms to nations. Today, the RISC-V community includes tens of thousands of engineers across 70 countries with members and contributions equally spread across the Americas, Europe, and Asia.
What is RISC-V?
RISC-V is a standard ISA that serves as a foundation for processor design. It enables communication and interoperability between hardware and software, providing a common language for software to control hardware through instructions like add, subtract, and multiply. Competitive differentiation is not at the ISA level of RISC-V. RISC-V is simply the connection between software and hardware, it does not determine what the implementation is. This is similar to Ethernet. Ethernet by itself is not the competitive implementation of what is on either end of that cable – Ethernet is simply the standard communication connection between two points.
Key points about RISC-V include:
- The RISC-V standard itself is not the competitive differentiator: Competition is in the implementation. The ISA is a publicly available standard such as USB, Ethernet, and Bluetooth, allowing anyone to build their own solutions based on the RISC-V standard.
- Design flexibility: RISC-V supports a broad ecosystem of open or proprietary intellectual property, giving developers the freedom to create custom solutions tailored to specific workloads.
- RISC-V continues to see massive growth and has already become the most prolific, globally adopted non-proprietary ISA standard in history, with more than 13 billion cores already in the market. An analyst report by The SHD Group indicates RISC-V SoC unit shipments are forecast to surge to 16.2B units, with revenues reaching $92B by 2030.
Advantages of RISC-V
- Global community: RISC-V is supported by a global community that collaborates on technical standards, driving innovation and fostering a diverse ecosystem. The global community has contributed publicly available IP to the creation of a shared set of extensions that may be used with the base ISA. None of the extensions are proprietary, they are all open and publicly available.
- Open collaboration: Open collaboration enables companies and developers to work together, sharing ideas and contributing to the evolution of the ISA and related extensions.
- RISC-V is a standard, not open source. The RISC-V ISA and extensions go through a robust governance process to be ratified and frozen. The modular approach of a frozen standard ISA and extensions guard against fragmentation while enabling innovation.
- Enhanced cybersecurity: Public review and scrutiny of the standard improves cybersecurity robustness and resilience.
- Economic and technological value: The open nature of RISC-V promotes competition and encourages investment in new technologies. RISC-V has innovation potential for anyone by enabling freedom of design, an aspect that is out of reach on any other architecture due to proprietary licensing models that restrict the ability to innovate.
Engagement of Nations in RISC-V
Invest locally, engage globally. It is important to invest in the talent, companies, and institutions that compose the fabric of local economies. For long-term strategic success, investments to spur local growth must come with an international mindset, enabling access and opportunity to global development partners, supply chain, markets, and more.
Several regions and countries are investing in RISC-V, with more evaluating RISC-V as an avenue to grow and build their digital economy. Examples include:
- Europe. RISC-V has become a bedrock for the European Processor Initiative and numerous European Commission grants stemming from the European Chips Act in stride with EU research conducted on the importance of open software and hardware as the region invests in design capabilities for high-performance processing as well as new industry partnerships such as Quintauris.
- United States. RISC-V began in a U.S. University lab, funded by U.S. industry as a standard ISA contributed to the public domain. The momentum in the U.S. has continued with adoption and significant investment by numerous multinational companies, universities, government agencies, start-ups, VCs, and more.
- India. India has actively engaged RISC-V in its renowned Shakti program as well as numerous national investment programs in academia and industry, most recently the Digital India RISC-V Microprocessor (DIR-V) program.
- China. Industry, research, and academia in China have contributed to the overall success of RISC-V including many areas of global collaboration as illustrated in the 2023 RISC-V Summit China.
- Israel. The Israel Innovation Authority has invested in RISC-V including a consortium called GenPro to develop Israeli processors based on RISC-V technology.
- Brazil. Brazil is gaining traction with its recent RISC-V announcements including joining RISC-V as a Premier Board level member and a formal collaboration between Instituto Eldorado and Barcelona Supercomputing Center.
- Pakistan. Hosted its first Semiconductor summit in April 2024 with investment in building RISC-V talent throughout training centers and universities.
Recently, there have been questions about U.S. engagement in RISC-V. U.S. companies, universities, public sector, and individuals have played a significant role in the development of RISC-V, contributing to its growth and direction. Similar to other standards, engagement is crucial for maintaining or building a technological edge and ensuring interests are represented in the global standards landscape.
- Impact of Restrictions: Limiting U.S. participation in RISC-V would negatively impact the country’s economic and technological interests, while also ceding influence in the global standards environment. Throughout history, the more any single country contributes to a standard, the more that country may influence the direction of the standard.
- BIS Interim Final Rule: The U.S. Bureau of Industry and Security (BIS) issued an interim final rule in September 2022 that resolved issues related to the release of certain technologies in standards development activities. Discussions with BIS continue to support the September 2022 interim final rule, and any revisions could have a much broader impact across the standards landscape.
- RISC-V International policies and procedures comply with all existing export control policies.
Role of RISC-V International
RISC-V International is the non-profit association responsible for overseeing the RISC-V community and governing the standard’s development. The organization plays a central role in fostering collaboration, innovation, and growth in the RISC-V ecosystem through:
- Technical Work Groups: Democratic governance of standard specifications and open discussions.
- Events and Workshops: Hosting summits, workshops, and expos to build community and share knowledge.
- Resources and Programs: Providing academic resources, developer boards, and advocacy programs to support the growth of the RISC-V community.
Summary
RISC-V represents a new era of processor innovation through open collaboration and design freedom. Its global adoption is a testament to the power of standards in driving technical innovation and fostering a vibrant ecosystem of developers and stakeholders. The U.S. should continue to embrace RISC-V, leveraging its strengths to engage in technical leadership and strengthen its position in the global semiconductor landscape.