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The setting of voluntary standards in engineering dates back more than a century. The release of RISC-V to the open community in 2015 – for both standardization and ongoing improvement through open collaboration – marked the first time the hardware community embraced open-source standards and collaboration at this level.
Ensuring long term access to, and development of, the RISC-V Instruction Set Architecture is a strategic choice. RISC-V International is wholly committed to design freedom, choice, and flexibility, and supports open architecture extensions to the RISC-V ISA. We do not support work on alternative versions of RISC-V.
Our process is modeled on decades of success demonstrated by the open source community. RISC-V International’s intellectual property is developed and contributed collectively by members, and governed by the terms of open source licenses. Once IP is provided globally in this way, it is permanently open and remains available for all.
Global success of any architecture is driven by the shared collective interest of a community. Open source and global standards have a long history of success because they have a license framework that ensures anyone, anywhere can have ongoing access to them.
Prof. Krste Asanović and graduate students Yunsup Lee and Andrew Waterman started the RISC-V instruction set in May 2010 as part of the Parallel Computing Laboratory (Par Lab) at UC Berkeley, of which Prof. David Patterson was Director. The Chisel hardware construction language that was used to design many RISC-V processors was also developed in the Par Lab. The Par Lab was a five-year project to advance parallel computing funded by Intel and Microsoft for $10M over 5 years, from 2008 to 2013 1. It also received funding from several other companies and the State of California. While the project overall did not have Federal funding, Yunsup Lee and Andrew Waterman received some funding from the DARPA POEM photonics project , which funded some of the processor implementation development (but not the RISC-V ISA). The funds were 6.1 basic research via MIT as prime contract with the International Computer Science Institute as the subcontract. All the projects in the Par Lab were open source using the Berkeley Software Distribution (BSD) license, including RISC-V and Chisel. The following report of the Par Lab is the first publication that describes the RISC-V instruction set:
For RISC-V, the UC Berkeley ParLab industrial sponsors provided the initial funding that was used to develop RISC-V. They didn’t explicitly ask for RISC-V itself, their interest was in parallel processing systems.
Beyond that first publication, major RISC-V milestones were the first tapeout of a RISC-V chip in 28nm FDSOI (donated by ST Microelectronics based in Switzerland) in 2011, publication of a paper on the benefits of open instruction sets in 2014 2, the first RISC-V Workshop held in January 2015, and the RISC-V Foundation launch later that year with 36 Founding Members.
The ISA specification itself (i.e., the encoding of the instruction set) was effectively put into the public domain when the ISA tech reports were published, though the actual tech report text (an expression of the specification) was later put under a Creative Commons license to allow it to be improved by external contributors including the RISC-V Foundation.
No patents were filed related to RISC-V in any of these projects, as the RISC-V ISA itself does not represent any new technology. The RISC-V ISA is based on computer architecture ideas that date back at least 40 years. RISC processor implementations—including some based on other open ISA standards— are widely available from various vendors worldwide.
The worldwide interest in RISC-V is not because it is a great new chip technology, the interest is because it is a global open standard to which software can be ported, and which allows anyone to freely develop their own hardware to run the software. RISC-V International does not manage or make available any open RISC-V implementations, only the standard specifications. RISC-V software is managed by the respective open source software projects.
Also see the original history article titled RISC-V Genealogy.
1 Patterson, D., Gannon, D. and Wrinn, M., 2013. The Berkeley Par Lab: Progress in the Parallel Computing Landscape. Microsoft Corporation.
2 Asanović, K. and Patterson, D. Instruction Sets Should Be Free: The Case For RISC-V (EECS-2014-146), August 6, 2014.
After the invention of RISC-V, many projects used it, including research programs funded by the Defense Advanced Research Projects Agency (DARPA), in many places and many companies. Open source standards provide great benefits to U.S. taxpayers in reducing the cost of advanced military system development, and also increases security by allowing the government to build their own trusted implementations at low cost. Note that several decades ago, the United States Air Force developed the open standard MIL-STD-1750 16-bit processor ISA for military applications for the same reasons (https://en.wikipedia.org/wiki/MIL-STD-1750A).
The UC Berkeley ASPIRE Lab succeeded the Par Lab, and was led by Krste Asanović. It lasted from 2013 to 2018 and led to the building of several RISC-V compatible microprocessors. It had funding from DARPA as well as from many companies. The DARPA funding was basic research funding (6.1 category).
Basic research funding to universities is largely for unrestricted research with permission to publically disseminate the results. This contract is the standard model for U.S. federal grants to universities, and allows for results from the funded work to be published in the open literature and made accessible to the public at large, worldwide. The government retains rights to use any technology developed in the research, but, unless explicitly stated, does not restrict the technology.
A related DARPA photonics program predates RISC-V and funded research at MIT in 2006. The research supported the development of integrated silicon photonics. Later stages of funding at MIT and Berkeley were used to build prototype chips, which included RISC-V cores as infrastructure to demonstrate the photonic links.
The ASPIRE Lab was funded by the DARPA Power Efficiency Revolution for Embedded Computing Technologies (PERFECT)program. The goal of the program was to develop revolutionary approaches as well as the technologies and techniques to provide the power efficiency required to enable embedded computing systems. Researchers used RISC-V based systems to demonstrate the ideas in that program.
In all of these funded projects, the RISC-V ISA specification and RISC-V open-source cores were not a contract deliverable. RISC-V was just the infrastructure separately developed to support the funded research.
While DARPA did not fund the original RISC-V ISA definition, DARPA funding played a significant role in its later development. The linked article on the SSITH Voting Machine and DOD presentation by Linton Salmon detail some of the areas where DARPA research continues to support RISC-V.
DARPA is currently funding a large set of programs around open-source hardware technology. RISC-V International has never had DARPA funding, nor pursued or received funding from any government.
The RISC-V Foundation (www.riscv.org) was founded in 2015 to build an open, collaborative community of software and hardware innovators based on the RISC-V ISA. The Foundation, a non-profit corporation controlled by its members, directed the development to drive the initial adoption of the RISC-V ISA.
In November 2018, the RISC-V Foundation announced a joint collaboration with the Linux Foundation. As part of this collaboration, the Linux Foundation provides operational, technical, and strategic support for RISC-V International, which may include member management, accounting, training programs, infrastructure tools, community outreach, marketing, legal, and other open standard services and expertise.
Across 2018-2019, the RISC-V community has reflected on the geo-political landscape and we have heard concerns from around the world that investment in RISC-V must come with IP access continuity to ensure a long-term strategic investment. We first mentioned our intentions to move at the December 2018 summit. Incorporation in Switzerland has the effect of calming concerns of political disruption to the open collaboration model. RISC-V International does not maintain any commercial interest in products or services as a non-profit, membership organization. There have not been any export restrictions on RISC-V in the US and we have complied with all US laws. The move does not circumvent any existing restrictions, but rather alleviates uncertainty going forward.
In March 2020, the RISC-V International Association was incorporated in Switzerland. Along with this, we shifted to a new, more inclusive membership structure. Members of RISC-V International have access to and participate in the development of the RISC-V ISA specification and extensions as well as related hardware and software. RISC-V has a Board of Directors composed of member representatives as well as a Technical Committee of work group leaders.
RISC-V International has not incorporated in Switzerland based on any one country, company, government, or event. This move is reflective of community concern and managing strategic risk for our community investing in RISC-V for the next 50+ years.
The IP contributed and produced by RISC-V International is held under industry and global standard licenses that are already open to leverage by any company regardless of jurisdiction. This licensing is a common open source approach to foster collaboration that is not tied to any geographic regulation. IP in the public domain has not been subject to export control.
We encourage organizations, individuals, and enthusiasts to join our ecosystem and together enable a new era of processor innovation through open standard and open source collaboration.
We send occasional news about RISC-V technical progress, news, and events.