This year’s RISC-V Summit Europe, taking place in Munich, Germany from Monday, June 24 – Friday, June 28, has already welcomed more than 700 attendees from 40 countries!
Attendees at the event represent industry, government, research, academia and ecosystem organizations from around the world. The packed agenda explores AI, automotive, embedded, IoT, space, security and much more, with keynotes and invited talks from some of the industry’s leading voices, including:
- Calista Redmond, CEO of RISC-V International
- Thomas Böhm, Senior Vice President & General Manager Microcontroller Automotive at Infineon Technologies
- Edward Wilford, Principal Analyst at Omdia
- Krste Asanović, Chief Architect at SiFive
- Larry Wikelius, Director at RISE
- Johanna Bähr, Research Associate at Fraunhofer AISEC
Additionally, RISC-V International announced that Andrea Gallo has joined as the organization’s new vice president of Technology. Gallo heads up all of the organization’s technical activities, with a mission to facilitate the technical vision, cultivate stakeholder engagement, and drive the strategy in a deeply engaged collaboration with RISC-V members across workgroups and committees. He is also tasked with growing the adoption of the RISC-V ISA.
“I am thrilled to join RISC-V International and be part of this incredible, vibrant community,” said Gallo. “RISC-V International is a world-class organization that is igniting change and opportunity around the globe. This member-driven ecosystem is unique in fostering innovation at an incredible pace, thanks to the energy of all contributors and the focus on software-driven hardware design. It is exciting to be part of the future on RISC-V.”
The Summit also features panels that will bring together experts to discuss the future of computing with RISC-V. From “Accelerating AI Innovation with RISC-V” to “How can Europe Engage More in RISC-V?”, this year’s panels dive into RISC-V’s growing momentum across industries and continents.
With more than 60 different organizations participating in the event as speakers or exhibitors, several are making headlines with big announcements, including:
RISC-V Ecosystem News
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- Andes Technology: Rain AI Unveils Andes Technology as Its RISC-V Partner
- Andes Technology: Andes Technology Announced the QiLai SoC and the Voyager Development Board
- Axiomise: Axiomise Heads to RISC-V Summit Europe June 25-27 in Munich
- Breker: Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification Coverage
- Codasip: Codasip Introduces Best-In-Class RISC-V Core for Power-Efficient Applications
- DeepComputing: World’s First RISC-V Laptop Gets a MASSIVE Upgrade and Equips With Ubuntu
- Esperanto Technologies: Esperanto Technologies and Rapidus Partner To Enable More Energy-Efficient Designs for the Coming “Post GPU Era”
- Lauterbach: Lauterbach Presents Leading Debug Solutions at the RISC-V Summit in Munich
- Maven Silicon: Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training Partner
- Semidynamics: Semidynamics Benchmarks 7bn Parameter Model on RISC-V AI IP
- SiFive: SiFive Announces 4th Generation of Popular Essential Product Line to Spur Innovation Across Embedded Applications
Follow RISC-V International and all the activities from RISC-V Summit Europe at @risc_v on X and on LinkedIn. At the show? Tag us and share your posts using #RISCVSummitEurope!
Sessions will be recorded and shared on the RISC-V YouTube Channel. Don’t forget to check it out!