Working with High-Level-Language Debuggers in RISC-V-Based Apps | Rafael Taubinger, Electronic Design
Debugging RISC-V apps can be exhaustive and at times ineffective. However, a high-level-language debugger offers shortcuts to boost efficiency and gives you complete... Read more.
Lauterbach supports Fraunhofer RISC-V functional safety core | Nick Flaherty, EENews Europe
Lauterbach’s debug tool now supports the EMSA5-FS functional safety processor core developed using the open RISC-V instruction set architecture.
EMSA5-FS was... Read more.
Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, Phoronix
In recent weeks Ubuntu developers have been working on bringing up and improving support for the Starfive VisionFive, which is one of the most promising "low-cost"... Read more.
Strong Showing for First Experimental RISC-V Supercomputer | Nicole Hemsoth, The Next Platform
A European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance.
More importantly,... Read more.
First RISC-V-Based System-on-Chip (SoC) FPGA Enters Mass Production | EE Journal
Microchip’s Mi-V ecosystem has enabled customers to ramp products based on PolarFire® devices more quickly, from prototypes to production.
The first SoC Field... Read more.
Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPS
MIPS recently announced that the company is pivoting to RISC-V and introduced its first MIPS products based on RISC-V, targeting automotive, 5G and wireless networking,... Read more.
$400m RISC-V design centre for Barcelona | Nick Flaherty, EE News Europe
Intel has teamed up with the Barcelona Supercomputing Centre to establish a lab to develop the next generation of zettascale supercomputers based around the RISC-V... Read more.
RISC-V Researchers publish new RISC-V SoC | Robin Mitchell, Electropages
As RISC-V continues to increase in popularity, more architecture implementations are being developed, and one research team has demonstrated a 3-stage pipeline RISC-V... Read more.
Linux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board | Michael Larabel, Phoronix
A few days ago the RISC-V pull request landed in Linux 5.19 with support for RISC-V 32-bit (RV32) binaries on RV64, enabling the new Svpbmt extension, and other... Read more.
SiFive RISC-V Sees Some Performance Improvements On Ubuntu 22.04 | Michael Larabel, Phoronix
While SiFive has sadly shutdown production on the current HiFive Unmatched development board in order to focus on new products expected later this year, those... Read more.