Learning Computer Architecture with a Visual Simulation of RISC-V Processors
Project Snapshot
This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle... Read more.
TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography
Project Snapshot
Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards... Read more.
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education
Project Snapshot
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor... Read more.
Simplifying Sail Simulations and Architectural Compatibility Testing
Greg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V... Read more.
TestRIG – Randomized Testing of RISC-V CPUs
TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the... Read more.
Towards an Integrated Matrix Extension: Workload Analysis of CNN Inference with QEMU TCG Plugings
Introduction
Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions... Read more.
Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class Cores
Tammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During his... Read more.
How to Share Your Work and See What Others Are Building On RISC-V
Hello RISC-V Community,
We’ve heard your feedback! Many of you expressed an interest in seeing RISC-V projects from around the world, as well as having the... Read more.