A RISC-V Based Accelerator for Post Quantum Cryptography
Project Snapshot
Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware... Read more.
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ Flow
Verification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances... Read more.
RISC-V: Shaping the Future of Mobility with Open Standards
The automotive industry gathered last week in Munich to drive the future of mobility forward, with a particular focus on compute and software, two of the most important... Read more.
Microchip’s PolarFire® SoC FPGA Meets Beagle Board: High-Performance SoC with BeagleV®-Fire
The BeagleV®-Fire board from BeagleBoard.org features Microchip’s PolarFire® SoCs, harnessing its RISC-V and FPGA technology, creating a powerful platform... Read more.
CVA6 RISC-V PMP Vulnerabilities against FIA
Project Snapshot
Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded... Read more.
Learning Computer Architecture with a Visual Simulation of RISC-V Processors
Project Snapshot
This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle... Read more.
TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based Cryptography
Project Snapshot
Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards... Read more.
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education
Project Snapshot
HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor... Read more.
Simplifying Sail Simulations and Architectural Compatibility Testing
Greg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V... Read more.
TestRIG – Randomized Testing of RISC-V CPUs
TestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the... Read more.