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RISC-V Based IoT Platform Development Using Green Hills Software
INTEL PATHFINDER FOR RISC-V: NEW CAPABILITIES AND A GROWING ECOSYSTEM | Intel Corporation
RISC-V: An Open-Source Churn In Computational Hardware Electronics – Part 2 | Dr Santhosh Onkar, Swarajya
Imperas and Andes collaborate to support RISC-V innovations | Andes Technology and Imperas Software
UniHiker education platform teaches STEM with Mind+ and Jupyter (in China) | Jean-Luc Aufranc, CNX Software
CEVA joins Intel Pathfinder for RISC-V programme | CEVA, New Electronics
Sipeed M1s DOCK is a tiny RISC-V dev board for $11 | Brad Linder, Liliputing
$10.80 RISC-V AIoT module supports Linux | Giorgio Mendoza, Linux Gizmos
Codasip and Intel bring RISC-V development to higher-education | Codasip
Is your career at RISK without RISC-V? | P R Sivakumar, Founder and CEO, Maven Silicon
Simon Davidmann President & CEO of Imperas Software elected as Chair of the OpenHW Verification Task Group
Solid Sands Announces Major New Enhancements to SuperGuard
Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem | Codasip
L’ESP32-C5 est la première puce-système RISC-V qui prend en charge le Wi-Fi 6 bibande et le Bluetooth LE | Pierrick Arlot, L’embarque.
An Introduction to Digi-Key’s RISC-V Reference Guide | Rich Miron, Digi-Key
Researchers Benchmark Experimental RISC-V Supercomputer | Anton Shilov, Tom’s Hardware
Microchip Pushes First RISC-V-based SoC FPGA to Mass Production | Jake Hertz, All About Circuits
Working with High-Level-Language Debuggers in RISC-V-Based Apps | Rafael Taubinger, Electronic Design
Lauterbach supports Fraunhofer RISC-V functional safety core | Nick Flaherty, EENews Europe
Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, Phoronix
Strong Showing for First Experimental RISC-V Supercomputer | Nicole Hemsoth, The Next Platform
First RISC-V-Based System-on-Chip (SoC) FPGA Enters Mass Production | EE Journal$400m RISC-V design centre for Barcelona | Nick Flaherty, EE News Europe
RISC-V Researchers publish new RISC-V SoC | Robin Mitchell, Electropages
RISC-V Based IoT Platform Development Using Green Hills SoftwareInternet of Things (IoT) applications are taking over more and more tasks in transportation, industrial and medical market segments. Developers are facing the challenge of…
INTEL PATHFINDER FOR RISC-V: NEW CAPABILITIES AND A GROWING ECOSYSTEM | Intel CorporationIntel® Pathfinder for RISC-V* is announcing an exciting array of new features to be released on December 12, 2022, while continuing to grow a healthy…
RISC-V: An Open-Source Churn In Computational Hardware Electronics – Part 2 | Dr Santhosh Onkar, SwarajyaThe previous article was a ‘look back’ at the computation paradigm and the context in which RISC-V has emerged as a new player. In this article, we…
Imperas and Andes collaborate to support RISC-V innovations | Andes Technology and Imperas SoftwareImperas reference models for Andes expanded with Andes Custom Extension™ support and design flow integration for leading EDA environments, plus new AndesCore® N25F-SE core for…
UniHiker education platform teaches STEM with Mind+ and Jupyter (in China) | Jean-Luc Aufranc, CNX SoftwareDFRobot UniHiker is a STEM education platform with a 2.8-inch touchscreen display, a Rockchip RK3308 quad-core Cortex-A35 processor, a GD32V RISC-V microcontroller, WiFi and Bluetooth…
CEVA joins Intel Pathfinder for RISC-V programme | CEVA, New ElectronicsCEVA, a licensor of wireless connectivity and smart sensing technologies, is to make its CEVA-BX1 and CEVA-BX2 Audio DSPs and audio front-end software stack available…
Sipeed M1s DOCK is a tiny RISC-V dev board for $11 | Brad Linder, LiliputingDisclosure: Some links on this page are monetized by the Skimlinks, Amazon, Rakuten Advertising, and eBay, affiliate programs. All prices are subject to change, and this article only reflects…
$10.80 RISC-V AIoT module supports Linux | Giorgio Mendoza, Linux GizmosThe Sipeed M1s is a compact module integrating the Bouffalo Lab BL808 RISC-V SoC module along with a NPU. The device also provides WiFi/BL, 802.15.4 Zigbee connectivity…
Codasip and Intel bring RISC-V development to higher-education | CodasipThe Codasip University Program joins Intel® Pathfinder For RISC-V Codasip, the leader in processor design automation and RISC-V processor IP, today announced it is collaborating…
Is your career at RISK without RISC-V? | P R Sivakumar, Founder and CEO, Maven SiliconI am delighted to share my technical insights into RISC-V in this article to inspire and prepare the next generation of chip designers for the…
Simon Davidmann President & CEO of Imperas Software elected as Chair of the OpenHW Verification Task GroupOxford, United Kingdom – December 5th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Simon Davidmann has been elected as Chair of…
Solid Sands Announces Major New Enhancements to SuperGuardAmsterdam, The Netherlands – December 2, 2022 – Solid Sands, the world-leading provider of testing and qualification technology for compilers and libraries, announces a major new…
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Codasip appoints Mike Eftimakis as VP of Strategy and Ecosystem | CodasipCodasip, the leader in customizable RISC-V processor IP, today announced it has appointed Mike Eftimakis as VP Strategy and Ecosystem. Mike Eftimakis has an extensive…
L’ESP32-C5 est la première puce-système RISC-V qui prend en charge le Wi-Fi 6 bibande et le Bluetooth LE | Pierrick Arlot, L’embarque.Connue pour ses puces-systèmes ESP32 compatibles Wi-Fi, Bluetooth et Bluetooth Low Energy et très présente sur le marché des objets connectés, la société Espressif Systems…
An Introduction to Digi-Key’s RISC-V Reference Guide | Rich Miron, Digi-KeyRISC-V (pronounced Risk Five) is a relatively new computer technology that is being actively promoted as a competitor to ARM. A guide has been written…
Researchers Benchmark Experimental RISC-V Supercomputer | Anton Shilov, Tom’s HardwareMonte Cimone cluster combines 32 RISC-V cores. A group of researchers from the Università di Bologna and Cineca has explored an experimental eight-node 32-core RISC-V…
Microchip Pushes First RISC-V-based SoC FPGA to Mass Production | Jake Hertz, All About CircuitsMicrochip continues the push for RISC-V hardware by reaching milestones with its PolarFire system-on-a-chip (SoC) field-programmable gate array (FPGA) and Mi-V ecosystem. One major trend…
Working with High-Level-Language Debuggers in RISC-V-Based Apps | Rafael Taubinger, Electronic DesignDebugging RISC-V apps can be exhaustive and at times ineffective. However, a high-level-language debugger offers shortcuts to boost efficiency and gives you complete control over…
Lauterbach supports Fraunhofer RISC-V functional safety core | Nick Flaherty, EENews EuropeLauterbach’s debug tool now supports the EMSA5-FS functional safety processor core developed using the open RISC-V instruction set architecture. EMSA5-FS was developed by Fraunhofer Institute…
Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, PhoronixIn recent weeks Ubuntu developers have been working on bringing up and improving support for the Starfive VisionFive, which is one of the most promising…
Strong Showing for First Experimental RISC-V Supercomputer | Nicole Hemsoth, The Next PlatformA European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance. More importantly, it demonstrates…
First RISC-V-Based System-on-Chip (SoC) FPGA Enters Mass Production | EE JournalMicrochip’s Mi-V ecosystem has enabled customers to ramp products based on PolarFire® devices more quickly, from prototypes to production. The first SoC Field Programmable Gate…
$400m RISC-V design centre for Barcelona | Nick Flaherty, EE News EuropeIntel has teamed up with the Barcelona Supercomputing Centre to establish a lab to develop the next generation of zettascale supercomputers based around the RISC-V…
RISC-V Researchers publish new RISC-V SoC | Robin Mitchell, ElectropagesAs RISC-V continues to increase in popularity, more architecture implementations are being developed, and one research team has demonstrated a 3-stage pipeline RISC-V SoC with…