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Imperas RISC-V Summit Kickoff Party, December 12 2022
RISC-V Summit 2022: Future Careers Start HereRISC-V Summit 2022: A Journey from Android to Outer Space … and Much More | RISC-V International
CAES Design Win of RISC-V/NOEL-V IP for Idaho Scientific Secure Processor for US Critical InfrastructureImperas and Andes collaborate to support RISC-V innovations
Cortus announces two new RISC-V microcontrollers (MCUs) Lotus family2022 RISC-V Summit Technical Tutorials Announced | RISC-V International
RISC-V开发板大派送，CNRV社区助你开启RISC-V创作之旅
11 Myths About Using Formal Verification
NASA Uses RISC-V Vector Spec to Soup Up Space Computers | Chenny Wang, EE Times
Secure-IC acquires Silex Insight’s security business to accelerate its chip-to-cloud plan and develop the next-generation of embedded cybersecurity solutions
RISC-V Is Thriving: Here’s What You Need To Know | Steve Brown, Semiconductor Engineering
Linux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board | Michael Larabel, PhoronixSiFive RISC-V Sees Some Performance Improvements On Ubuntu 22.04 | Michael Larabel, Phoronix
CAES and Ashling Announce Ashling’s RiscFree™ C/C++ Toolchain for CAES’ NOEL-V® Processors | Ashling, Business Wire
Intel investing in RISC-V Architecture for its Zettascale Supercomputers Chips | Nivedita Bangari, Technosports
First samples for RISC-V and ARM embedded modules | Nick Flaherty, EE News Europe
Yeah, RISC-V Is Actually a Good Design | Erik Engheim, ITNEXT
NSITEXE Selects ImperasDV for Automotive Quality RISC-V Processor Functional Design Verification | Imperas SoftwareAshling to provide RiscFree™ RISC-V Toolchain support for Intel FPGAs | Ashling, Business Wire
HPCwire‘s People to Watch Program | HPCWire
MIPS Chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA Compatible IP Cores | Ashling and MIPS, BusinessWire
RISC-V is coming to the internet of things | Stacey Higginbotham, Stacey on IoT
SEGGER releases new Embedded Studio for RISC-V with hard real-time C++ support | SEGGER, Electronic Engineering Journal
Imperas RISC-V Summit Kickoff Party, December 12 2022Imperas Software Ltd., the leader in RISC-V models and simulation solutions, today announced the Imperas RISC-V Summit Kickoff Party 2022. Start off the RISC-V Summit…
RISC-V Summit 2022: Future Careers Start HereRecent technology sector headlines have focused on companies implementing hiring freezes and layoffs – but the RISC-V ecosystem tells a different story: one of growth…
RISC-V Summit 2022: A Journey from Android to Outer Space … and Much More | RISC-V International2022 has been an incredible year for RISC-V, the open-standard Instruction Set Architecture (ISA) that is unleashing a new wave of innovation in computing. With…
CAES Design Win of RISC-V/NOEL-V IP for Idaho Scientific Secure Processor for US Critical InfrastructureCAES, a leader in advanced mission-critical electronics for aerospace and defense, announced that it has won its first commercial U.S.-based license for its RISC-V/NOEL-V processor IP with Idaho…
Imperas and Andes collaborate to support RISC-V innovationsOxford, United Kingdom – November 29th, 2022 – Imperas Software Ltd., the leader in RISC-V simulation solutions, today announced that Andes Technology Corp., a leading supplier of performance-efficient and…
Cortus announces two new RISC-V microcontrollers (MCUs) Lotus familyMontpellier, France – November 28, 2022 – Cortus, an innovative French fabless semiconductor manufacturing group today announces two new RISC-V microcontrollers (MCUs). They are designed…
2022 RISC-V Summit Technical Tutorials Announced | RISC-V InternationalThis past month, the RISC-V Summit 2022 schedule was announced. The Summit, which will be held on December 12-14, 2022, is the industry’s leading RISC-V…
RISC-V开发板大派送，CNRV社区助你开启RISC-V创作之旅CNRV社区在农历新年来临还有2个月之际推出免费派送RISC-V开发板活动，这对希望能够实际操作RISC-V设备的学生群体以及所有RISC-V爱好者是一个不容错过的机会。通过此次派送活动，CNRV希望能够提高中国境内设计制造RISC-V设备的社区活跃度，让更多志同道合的RISC-V爱好者参与其中，完善社区生态。同时，CNRV社区不仅是在当下更将是在未来，会为推动RISC-V的繁荣，促进全球软件生态的发展贡献一份力，承担一份责。 本次活动共派送64块支持Linux系统的LicheeRV 1GB内存开发板。活动若出现超过64位合格申请者的情况，将通过PR被合并的次序来确定人选，同一批审核通过的PR按照提交ID排序合入。主办方希望在2023年1月23日前发放完毕，考虑到物流因素，请尽量于2023年1月2日完成您的Proposal。 报名方式 Fork cnrv/riscv-innovations 仓库；复制2022Q4-LicheeRV-Hacks/Proposal_Template.md并以自己的Github ID命名；填写模版里的内容；发起PR。 CNRV组织方会在5天内审核PR，在给出反馈意见后或进行必要修改，形式要件满足后会合并PR。 合并完成后主办方会通过非公开的渠道（邮件/微信/百格表单）获取您的快递信息。（注意本次活动可供邮寄地址仅限于中国大陆） 填写邮寄地址大概一周后，您将会收到一块LicheeRV 1GB内存开发板。 Happy Hacking！等您完成工作之后，发起一个新的PR，将成果的链接追加到自己的Proposal末尾即可。 开源只有参与进去，才能体会到其中的乐趣。想开阔你的技术视野提升你的技术能力吗？想继续与社区强者获得更广泛的交流进行思想碰撞吗？提交你的PR！CNRV社区或许能让你拥有第一块RISC-V开发板，完成你的开发与测试，实现你的奇思妙想，创造属于你的价值。为RISC-V中国、开源社区添砖加瓦，还缺你一个！欢迎你的加入，期待见到你的PR！ 关于CNRV CNRV社区为中国的RISC-V开发者和爱好者提供了一个交流与学习、合作并创新的平台。同时CNRV也是RISC-V中国峰会协办方，通过社区和峰会传播与交流RISC-V相关技术信息、学习研究成果，全面推动RISC-V在中国的发展。了解更多信息请关注CNRV微信公众号。 加入CNRV，关注CNRV公众号（ID：risc-v）。 加入CNRV社群，添加组织者微信fangzhang1024（请备注）
11 Myths About Using Formal VerificationAxiomise’s Dr. Ashish Darbari dispels a host of myths to highlight the advantages of formal verification for IC design. What you’ll learn: How formal verification…
NASA Uses RISC-V Vector Spec to Soup Up Space Computers | Chenny Wang, EE TimesWith the growing demand for applications that require multiple cores and AI, ML, and computer vision capabilities, faster and power-efficient processing is essential. At the…
Secure-IC acquires Silex Insight’s security business to accelerate its chip-to-cloud plan and develop the next-generation of embedded cybersecurity solutionsThe RISC-V member @Secure-IC has announce the acquisition of @Silex Insight security business (also a RISC-V member) to accelerate its Chip-To-Cloud plan and develop the…
RISC-V Is Thriving: Here’s What You Need To Know | Steve Brown, Semiconductor EngineeringRISC-V, the open-standard Instruction Set Architecture (ISA) conceived by UC Berkeley developers in 2010, is going from strength to strength. The RISC in RISC-V stands…
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Linux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board | Michael Larabel, PhoronixA few days ago the RISC-V pull request landed in Linux 5.19 with support for RISC-V 32-bit (RV32) binaries on RV64, enabling the new Svpbmt extension,…
SiFive RISC-V Sees Some Performance Improvements On Ubuntu 22.04 | Michael Larabel, PhoronixWhile SiFive has sadly shutdown production on the current HiFive Unmatched development board in order to focus on new products expected later this year, those with a…
CAES and Ashling Announce Ashling’s RiscFree™ C/C++ Toolchain for CAES’ NOEL-V® Processors | Ashling, Business WireAshling and CAES announced today that Ashling’s RiscFree Toolchain will provide software development support for CAES’ NOEL-V fault tolerant RISC-V based processors. NOEL-V is a synthesizable VHDL…
Intel investing in RISC-V Architecture for its Zettascale Supercomputers Chips | Nivedita Bangari, TechnosportsThis week, Intel and the Barcelona Supercomputing Centre (BSC) announced a €400 million (about $426 million) investment in a laboratory to create RISC-V-based processors that…
First samples for RISC-V and ARM embedded modules | Nick Flaherty, EE News EuropeAries Embedded has received first samples of its latest RISC-V and ARM-based embedded system-in-package boards ready to show for the first time later this month. The MSRZG2UL…
Yeah, RISC-V Is Actually a Good Design | Erik Engheim, ITNEXTWell known people in the industry such as Dave Jaggar, Jim B. Keller and Dave Ditzel give RISC-V the thumbs up. The more I write…
NSITEXE Selects ImperasDV for Automotive Quality RISC-V Processor Functional Design Verification | Imperas SoftwareImperas RISC-V Reference Model, Test suites and Verification IP for advanced ‘lock-step-compare’ Processor Verification including Asynchronous events and Coverage Analysis. Imperas Software Ltd., the leader in…
Ashling to provide RiscFree™ RISC-V Toolchain support for Intel FPGAs | Ashling, Business WireAshling has announced that Ashling’s RiscFree Toolchain will provide support for Intel FPGAs including Intel’s Nios V Processor later this year. “Intel is pleased to…
HPCwire‘s People to Watch Program | HPCWire2022 marks the 20th year of HPCwire‘s People to Watch Program, which recognizes HPC professionals who play leading roles in driving innovation within their particular fields,…
MIPS Chooses Ashling’s RiscFree™ Toolchain for its RISC-V ISA Compatible IP Cores | Ashling and MIPS, BusinessWireAshling and MIPS announced today that Ashling’s RiscFree™ Toolchain has been extended to support MIPS RISC-V ISA based IP cores. RiscFree™ is Ashling’s Integrated Development Environment (IDE) including a…
RISC-V is coming to the internet of things | Stacey Higginbotham, Stacey on IoTFans of this newsletter know I’m a major chip nerd. I started my tech career as a semiconductor reporter, and for the last seven or…
SEGGER releases new Embedded Studio for RISC-V with hard real-time C++ support | SEGGER, Electronic Engineering JournalSEGGER’s Embedded Studio for RISC-V, Version 6, now uses real-time memory management which improves efficiency and response time when allocating and freeing up memory, satisfying requirements…