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SiFive launches Performance P670 and P470 RISC-V energy efficient processors | Bogdan Solca, Notebook Check
Codasip, SiliconArts team on RISC-V ray tracing graphics IP | Nick Flaherty, EE News Europe
SEGGER introduces streaming trace probe for SiFive RISC-V cores | SEGGER
Open source TileLink to AHB bridges with dedicated Cocotb extensions | Antmicro
Lilbits: RISC-V and de-Googled phones, and Qualcomm sees 2024 as the year of the Snapdragon-powered PC | Brad Linder, Liliputing
Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications | Jean-Luc Aufranc, CNX SoftwareAndroid Open Source Project ports to RISC-V | Nick Flaherty, EE News Europe
XuanTie C908: High-performance RISC-V Processor Catered to AIoT Industry | Chang Liu, Alibaba CloudSiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions | Jean-Luc Aufranc, CNX Software
With its New RISC-V Processors, SiFive Bets on Compute Density | Jeff Child, All About Circuits
SiFive Reveals New RISC-V Chips, the P670 and P470 | Ian Evenden, Tom’s Hardware
Registration for the In-person RVfpga Session at the 2022 RISC-V Summit is Open. Space is Limited! | Imagination Technologies
RISC-V Gets Sv57-Based Virtual Memory, Other Improvements For Linux 5.18 | Michael Larabel, Phoronix
Now the V in RISC-V Stands for VROOM! | Matthew Carlson, HackadayDongshan Nezha STU devkit features Allwinner D1 RISC-V SoM/SBC | Jean-Luc Aufranc, CNX Software
Adafruit’s QT Py ESP32-C3, Its First RISC-V Dev Board, Begins Rolling Off the Production Line | Gareth Halfacree, Hackster.io
CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology | Daniel Nenni, SemiWiki
Alphawave IP Announces Definitive Agreement to Acquire Entire OpenFive Business Unit from SiFive for US$210m in cash | Design and Reuse
IAR extends powerful RISC-V solutions with 64-bit support | IAR Systems
Intel Foundry Services Going Big On RISC-V ‘Brawny Cores’ With Ventana Micro Systems Compute Tiles | Patrick Moorhead, Forbes
Exploring emerging trends and topics in RISC-V architecture | Mouser Electronics, ElectroPages
Imperas unifies new RISC-V verification ecosystem with RVVI | Imperas
Mouser Electronics Launches 2022 Empowering Innovation Together Program with New Podcast on RISC-V | Raymond Yin, Business Wire
SEGGER collaboration makes Embedded Studio for RISC-V available at no cost | Neil Tyler, New Electronics
SiFive launches Performance P670 and P470 RISC-V energy efficient processors | Bogdan Solca, Notebook CheckWith the release of the P670 and P470 RISC-V processors, SiFive plans to deliver competitive alternatives to legacy technologies for the wearables, smart home and…
Codasip, SiliconArts team on RISC-V ray tracing graphics IP | Nick Flaherty, EE News EuropeA high end ray tracing graphics core is shipping with a customisable RISC-V core from German developer Codasip as the first step to integrated low…
SEGGER introduces streaming trace probe for SiFive RISC-V cores | SEGGERSEGGER’s J-Trace PRO with streaming trace, Live Code Profiling, and Live Code Coverage now supports all E-Series SiFive RISC-V cores with the BTM trace module. J-Trace PRO RISC-V, with its…
Open source TileLink to AHB bridges with dedicated Cocotb extensions | AntmicroAntmicro uses open source to introduce pragmatic innovation into areas which have traditionally been heavily reliant on proprietary technologies such as ASIC and FPGA. Due…
Lilbits: RISC-V and de-Googled phones, and Qualcomm sees 2024 as the year of the Snapdragon-powered PC | Brad Linder, LiliputingMicrosoft’s new Windows Dev Kit 2023 is a $600 mini PC with 32GB of RAM, a 512GB PCIe NVMe SSD, and the most powerful Qualcomm Snapdragon processor…
Andes unveils AndesCore AX65 Out-of-Order RISC-V core for compute intensive applications | Jean-Luc Aufranc, CNX SoftwareAndes Technology has unveiled the high-end AndesCore AX60 series out-of-order 64-bit RISC-V processors at the Linley Fall Processor Conference 2022 with the new cores designed…
Android Open Source Project ports to RISC-V | Nick Flaherty, EE News EuropeThe Android Open Source Project (AOSP) has been ported to the RISC-V processor architecture in a key move for the technology. Upstream enablement of RISC-V…
XuanTie C908: High-performance RISC-V Processor Catered to AIoT Industry | Chang Liu, Alibaba CloudXuanTie C908 is the latest RISC-V processor of the XuanTie series launched by T-Head Semiconductor. It has adopted the RV64GCB instruction and is compatible with…
SiFive P670 and P470 RISC-V processors feature RISC-V Vector Extensions | Jean-Luc Aufranc, CNX SoftwareSiFive has announced two new RISC-V Performance cores with the P670 and P470 processors with RISC-V Vector Extension for AI/ML, media and sensor processing, and…
With its New RISC-V Processors, SiFive Bets on Compute Density | Jeff Child, All About CircuitsAiming to usurp Arm processors in size-constrained, compute hungry designs like wearables, SiFive has expanded its RISC-V “Performance” line of processors. The momentum for RISC-V…
SiFive Reveals New RISC-V Chips, the P670 and P470 | Ian Evenden, Tom’s HardwareSiFive announced a pair(opens in new tab) of new high-performance RISC-V(opens in new tab) processors aimed at what it calls "next-generation wearables and smart consumer devices." Known as the…
Registration for the In-person RVfpga Session at the 2022 RISC-V Summit is Open. Space is Limited! | Imagination TechnologiesOnline is convenient and it has saved us during the pandemic, but you can’t beat in-person class! That immersive feeling of hands-on and the shared…
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RISC-V Gets Sv57-Based Virtual Memory, Other Improvements For Linux 5.18 | Michael Larabel, PhoronixThe RISC-V CPU architecture updates have landed for the in-development Linux 5.18 kernel. Notable with the RISC-V additions for Linux 5.18 is sv57 support for 5-level page tables.…
Now the V in RISC-V Stands for VROOM! | Matthew Carlson, HackadayHundreds of variations of open-source CPUs written in an HDL seem to float around the internet these days (and that’s a great thing). Many are…
Dongshan Nezha STU devkit features Allwinner D1 RISC-V SoM/SBC | Jean-Luc Aufranc, CNX SoftwareDongshan Nezha STU is a development kit comprised of an Allwinner D1 RISC-V system-on-module (SoM) and a carrier board with three 40-pin headers to access…
Adafruit’s QT Py ESP32-C3, Its First RISC-V Dev Board, Begins Rolling Off the Production Line | Gareth Halfacree, Hackster.ioAdafruit has confirmed that its QT Py ESP32-C3, the company's first development board built around the free and open source RISC-V instruction set architecture, is…
CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology | Daniel Nenni, SemiWikiFrankwell Lin, Chairman of Andes Technology, started his career being as application engineer in United Microelectronics Corporation (UMC) while UMC was an IDM with its own…
Alphawave IP Announces Definitive Agreement to Acquire Entire OpenFive Business Unit from SiFive for US$210m in cash | Design and ReuseTransaction will accelerate Alphawave’s connectivity leadership, product offerings and customer base while driving higher scale and revenue growth from an expanded total addressable market. Alphawave…
IAR extends powerful RISC-V solutions with 64-bit support | IAR SystemsIAR Systems extends powerful RISC-V solutions with 64-bit support. Bringing high-performance, well-established technology to companies choosing the emerging RISC-V 64-bit cores for their upcoming development…
Intel Foundry Services Going Big On RISC-V ‘Brawny Cores’ With Ventana Micro Systems Compute Tiles | Patrick Moorhead, ForbesIntel has made a considerable amount of strategic announcements in the past month, whether it be its Tower Semi acquisition, its $20B Ohio investment or…
Exploring emerging trends and topics in RISC-V architecture | Mouser Electronics, ElectroPagesMouser has launched the 2022 series of its Empowering Innovation Together program. This year's series comprises six instalments that spotlight a leading-edge technology that is…
Imperas unifies new RISC-V verification ecosystem with RVVI | ImperasNew open standard RISC-V Verification Interface (RVVI) offers adaptability and verification IP reuse for the expanding community of developers undertaking processor verification. Imperas Software Ltd., the…
Mouser Electronics Launches 2022 Empowering Innovation Together Program with New Podcast on RISC-V | Raymond Yin, Business WireThe first installment of Mouser's 2022 Empowering Innovation Together program zeroes in on RISC-V, including a new episode of The Tech Between Us podcast. Mouser…
SEGGER collaboration makes Embedded Studio for RISC-V available at no cost | Neil Tyler, New ElectronicsThe partnership is focusing on making SEGGER’s multi-platform IDE Embedded Studio available, free of charge, to all HPMicro’s customers using HPM6000 series RISC-V microcontrollers, boosting…