5 Ways Automakers Lose Control of Software, and How Open Standards Bring It Back
Codethink's Paul Sherwood shares his experience on how automakers lose control of software, and how open standards like RISC-V restore independence.
5 Ways Automakers Lose Control of Software, and How Open Standards Bring It BackCodethink's Paul Sherwood shares his experience on how automakers lose control of software, and how open standards like RISC-V restore independence.
Community Motion: What Are RISC-V Advocates Doing?There are plenty of ways to contribute to the RISC-V community. From organizing community events to writing, speaking, building technical communities, and growing RISC-V in…
V Questions with… Maven Silicon’s P R ‘Siva’ SivakumarMaven Silicon CEO P R Sivakumar on using RISC-V to bridge the skills gap, building a stronger engineering community and preparing new talent for an…
Monte Cimone v3: Where RISC-V Stands in High-Performance ComputingProject Snapshot The Monte Cimone project is a RISC-V-based testbed for High-Performance Computing (HPC) clusters. This work presents Monte Cimone v3 (MCv3), the third iteration…
V Questions with… Openchip’s Cesc Guim and Marc Fernández'V Questions with…' uncovers the backstory to a RISC-V member's latest work in 5 questions. Here, I talk to the duo behind BER10, the sovereign…
For Automakers, RISC-V Isn’t Just About Ownership: It’s About Freedom of ChoiceMIPS’ Sameer Wasson explains why an automotive OEM’s choice of instruction set architecture (ISA) should prioritize supplier choice, software reuse and long-term economic control.
Integration Challenges in RISC-V System Prototyping: The RISER Microserver PlatformProject Snapshot This blog post reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V…
Martin Fink’s Ferrite Engineering Lifts the Lid on ‘Schrödinger’s Instruction’EDACrux, offered free to the RISC-V ecosystem, serves to demonstrate how success is built upon our members’ commitment to openness.
Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SWProject Snapshot Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified…
RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart GlassesProject Snapshot This live demonstration showcases GAPses, an ultra-low-power smart-glasses platform based on an ultra-low power RISC-V multicore processor (GAP9), enabling always-on, real-time, energy-efficient edge…
Behind The Scenes of SHD Group’s 2026 RISC-V Market ForecastHaving spent much of my career flying the flag for B2B tech, I know that belief in the thing you’re championing runs deeper than commercial…
Call for Candidates: Help Us Build a Board That Represents Our Entire EcosystemVoting is now open for RISC-V International's Board of Directors. Learn how to nominate, understand board member responsibilities, and discover key election dates.
Community Motion: What Are RISC-V Advocates Doing?There are plenty of ways to contribute to the RISC-V community. From organizing community events to writing, speaking, building technical communities, and growing RISC-V in…
Martin Fink’s Ferrite Engineering Lifts the Lid on ‘Schrödinger’s Instruction’EDACrux, offered free to the RISC-V ecosystem, serves to demonstrate how success is built upon our members’ commitment to openness.
Behind The Scenes of SHD Group’s 2026 RISC-V Market ForecastHaving spent much of my career flying the flag for B2B tech, I know that belief in the thing you’re championing runs deeper than commercial…
Call for Candidates: Help Us Build a Board That Represents Our Entire EcosystemVoting is now open for RISC-V International's Board of Directors. Learn how to nominate, understand board member responsibilities, and discover key election dates.
We Created a Single Source for All RISC-V SpecificationsThe RISC-V Ratified Specifications Library consolidates all of the available RISC-V specifications into one single, accessible repository.
Production-Ready, Automotive-Grade, AI-Native: RISC-V at Embedded World 2026Ahead of Embedded World, we explore what our members and co-exhibitors will showcase in Nuremberg, the common threads linking their work, and what this reveals…
Start Porting Software To RISC-V Today With Our New, Free Online CoursePorting Software to RISC-V (LFD114) is our free course for experienced engineers who need to move performance-critical software to RISC-V.
Introducing the RISCstar Toolchain for RISC-VThe newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter StatusAt RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded DevicesAt RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…
New Course Coming Soon: Porting Software to RISC-V (LFD 114)The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…
Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor ProjectThe eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…
Community Motion: What Are RISC-V Advocates Doing?There are plenty of ways to contribute to the RISC-V community. From organizing community events to writing, speaking, building technical communities, and growing RISC-V in…
Announcing the 2025 AI & RISC-V Gemini Credit RecipientsAnd the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ FlowVerification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
New to RISC-V? Here’s Why Summit 2025 is the Place to Begin Your JourneyThe 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
RISC-V: The AI-Native Platform for the Next Trillion Dollars of ComputeWe explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Design Approaches and Architectures of RISC-V SoCsAuthor: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
From Simulation Bottlenecks to Formal Confidence: Leveraging Formal for Exhaustive RISC-V VerificationIntroduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
Arteris’ Multi-Die Solution for the RISC-V Ecosystemby Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
RISC-V Summit China 2025: Reflections from a RISC-V Software ContributorBy Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
Certifying Embedded Applications Running on PolarFire® SoC FPGAsBy: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
Cost-Effective and Scalable: A Smarter Choice for RISC-V DevelopmentThe RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…
Monte Cimone v3: Where RISC-V Stands in High-Performance ComputingProject Snapshot The Monte Cimone project is a RISC-V-based testbed for High-Performance Computing (HPC) clusters. This work presents Monte Cimone v3 (MCv3), the third iteration…
Integration Challenges in RISC-V System Prototyping: The RISER Microserver PlatformProject Snapshot This blog post reports on the experiences and roadmap of the RISER project, which since January 2023 has been developing first-generation all-European RISC-V…
Conflict to Compliance: RISC-V Extension Migration Across Spec, HW, and SWProject Snapshot Non-compliant RISC-V extensions remain a practical obstacle for custom and legacy CPU designs. We present a two-phase workflow that uses the RISC-V Unified…
RISC-V Edge Inference for Real-Time Eye-Movement Control on GAPses Smart GlassesProject Snapshot This live demonstration showcases GAPses, an ultra-low-power smart-glasses platform based on an ultra-low power RISC-V multicore processor (GAP9), enabling always-on, real-time, energy-efficient edge…
Docker on RISC-V: From Release to Production in 6 DaysProject Snapshot Community-maintained Docker packages bring v29 to RISC-V64 within days of official release, not months. Fully automated pipelines compile natively on RISC-V hardware, delivering…
Using a Performance Model to Implement a Superscalar CVA6Project Snapshot How does performance modeling accelerate real hardware innovation in open RISC-V designs? In this paper, Thales demonstrates a performance model of the CVA6…
Support RAJA and Scientific Applications on RVV ArchitecturesProject Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is…
How We’re Using AI to Streamline RISC-V Regression DebuggingAI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.
Ocelot3: Full Vector “V” Extension for BOOMProject Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The…
Enabling High Performance RISC-V Software for AI in the Real WorldEmbecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
Optimizing Hardware for Neural Network Inference using Virtual PrototypesProject Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…
A RISC-V Based Accelerator for Post Quantum CryptographyProject Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware…
Community Motion: What Are RISC-V Advocates Doing?There are plenty of ways to contribute to the RISC-V community. From organizing community events to writing, speaking, building technical communities, and growing RISC-V in…
Announcing the 2025 AI & RISC-V Gemini Credit RecipientsAnd the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ FlowVerification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
New to RISC-V? Here’s Why Summit 2025 is the Place to Begin Your JourneyThe 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
RISC-V: The AI-Native Platform for the Next Trillion Dollars of ComputeWe explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Design Approaches and Architectures of RISC-V SoCsAuthor: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
From Simulation Bottlenecks to Formal Confidence: Leveraging Formal for Exhaustive RISC-V VerificationIntroduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
Arteris’ Multi-Die Solution for the RISC-V Ecosystemby Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
RISC-V Summit China 2025: Reflections from a RISC-V Software ContributorBy Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
Certifying Embedded Applications Running on PolarFire® SoC FPGAsBy: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
Cost-Effective and Scalable: A Smarter Choice for RISC-V DevelopmentThe RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…