No recent posts listed
Imperas Announces Partnership with Breker to Drive Rigorous Processor-to-System Level Verification for RISC-V | Imperas Software
seL4 userspace debugging with GDB extensions in Renode | Antmicro
PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | MicrochipImperas announce the latest RISC-V test suites are now available free with riscvOVPsimPlus | Imperas Software
Upcoming RISC-V laptop promises free silicon upgrades | Scharon Harding, Ars Technica
First RISC-V laptop arrives | Nick Farrell, Fudzilla
TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms | Semiconductor Engineering
Take note, Arm: The world’s first RISC-V laptop is now available for preorder | Joel Khalili, Tech Radar
First native RISC-V laptop readies for market | Nick Flaherty, EE News Europe
The first laptop with a RISC-V processor is coming | Brad Linder, Liliputing
One of the first RISC-V laptops may ship in September, has an NFT hook | Dylan Martin, The Register
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep Computing
Tutorial: Vortex tutorials at MICRO-54 (Oct 18 2021) | Hyesoon Kim, Blaise Tine, Ruobing Han, Liam Cooper, and Jeff Young, Georgia Institute of Technology
My experience installing Libero SoC in Ubuntu and Windows 10 | Jean-Luc Aufranc, CNX Software
GCC 12 Merges Initial Support For RISC-V’s Bitmanip Extensions | Michael Larabel, PhoronixRISC-V starts to put pressure: 16-core CPU and performance superior to Cortex-A78 | Deepak Gupta, Tech Unwrapped
Alibaba Cloud pushes into South Korea, Thailand with faster, more efficient data centers | Peter Cohen, RCR Wireless News
IAR Systems Extends Functional Safety Offering for RISC-V with Build Tools for Linux | Tiera Oliver, Embedded Computing Design
Allwinner D1s/F133 RISC-V processor integrates 64MB DDR2 | Jean-Luc Aufranc, CNX Software
IAR Systems extends functional safety offering for RISC-V with leading build tools for Linux | IAR SystemsA Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications | Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, and Saponara Sergio, IEEE Transactions on Emerging Topics in Computing
Video: Accelerating Neural Networks using RISC-V and Open Standard Software | Charles Macfarlane, Codeplay Software
SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes | Anton Shilov, Tom’s Hardware
ETH Zurich Team Unveils RISC-V-Based Snitch Processor, Boasts of Sixfold Performance Gains | Gareth Halfacree, Hackster.io
Imperas Announces Partnership with Breker to Drive Rigorous Processor-to-System Level Verification for RISC-V | Imperas SoftwareImperas Software Ltd., the leader in RISC-V simulation solutions, today announced a partnership with Breker Verification Systems, a leading provider of advanced test content synthesis solutions for…
seL4 userspace debugging with GDB extensions in Renode | AntmicroDebugging is an integral part of the embedded systems development process especially in the context of userspace applications running inside an OS, where it can…
PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | MicrochipOperational Technology (OT) and Transportation and Industrial Control Systems (ICS) are often forced to make concessions regarding security and updates to deliver critical functionality without…
Imperas announce the latest RISC-V test suites are now available free with riscvOVPsimPlus | Imperas SoftwareImperas Software Ltd., the leader in RISC-V simulation solutions, today announced the latest RISC-V test suites and updates to the free riscvOVPsimPlus reference model, simulator and test suites.…
Upcoming RISC-V laptop promises free silicon upgrades | Scharon Harding, Ars TechnicaThe world's first laptop to use the RISC-V open source instruction set architecture (ISA) will reportedly start shipping in September. The Roma laptop is available for…
First RISC-V laptop arrives | Nick Farrell, FudzillaThe world’s first RISC-V laptop has just hit the shelves to a collective yawn from reviewers. The ROMA development platform boasts the forthcoming quad-core RISC-V…
TU Dresden: Tile-based Multi-Core Architecture for Heterogeneous RISC-V Processors Suitable for FPGA Platforms | Semiconductor EngineeringNew technical paper titled “AGILER: An Adaptive Heterogeneous Tile-Based Many-Core Architecture for RISC-V Processors” from researchers at Technische Universitaet Dresden (TU Dresden). Read the full…
Take note, Arm: The world’s first RISC-V laptop is now available for preorder | Joel Khalili, Tech RadarA new laptop billed as the first ever to run atop RISC-V-based silicon is now available to pre-order (opens in new tab) online. The product…
First native RISC-V laptop readies for market | Nick Flaherty, EE News EuropeARM has spent decades working with partners on ARM-based laptops. Its open standard competitor, RISC-V, is looking to catch up fast with the first developers…
The first laptop with a RISC-V processor is coming | Brad Linder, LiliputingThe first laptop powered by a processor that uses RISC-V architecture is up for pre-order. The “Roma” laptop comes from a collaboration between China’s DeepComputing…
One of the first RISC-V laptops may ship in September, has an NFT hook | Dylan Martin, The RegisterIt seems promoters of RISC-V weren't bluffing when they hinted a laptop using the open-source instruction set architecture would arrive this year. Pre-orders opened Friday…
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep ComputingROMA development platform features forthcoming quad-core RISC-V processor for fastest, seamless RISC-V software development experience. DeepComputing and Xcalibyte today opened pre-orders for the industry’s first…
No recent posts listed
No recent posts listed
No recent posts listed
No recent posts listed
Tutorial: Vortex tutorials at MICRO-54 (Oct 18 2021) | Hyesoon Kim, Blaise Tine, Ruobing Han, Liam Cooper, and Jeff Young, Georgia Institute of TechnologyVortex is an open source Hardware and Software project to support GPGPU based on RISC-V ISA extensions. Currently Vortex supports OpenCL/CUDA and it runs on…
My experience installing Libero SoC in Ubuntu and Windows 10 | Jean-Luc Aufranc, CNX SoftwareA few weeks ago, I received Microchip PolarFire SoC FPGA Icicle Kit with FPGA fabric and hard RISC-V cores capable of handling Linux. I wrote…
GCC 12 Merges Initial Support For RISC-V’s Bitmanip Extensions | Michael Larabel, PhoronixFollowing the recent RISC-V Bitmanip work in Binutils, the GCC 12 compiler has now landed preliminary support for the RISC-V ISA's bit manipulation extension. RISC-V's…
RISC-V starts to put pressure: 16-core CPU and performance superior to Cortex-A78 | Deepak Gupta, Tech UnwrappedSiFive has become, thanks to the RISC-V architecture, one of the most promising companies in the semiconductor world. We are not talking about a newcomer,…
Alibaba Cloud pushes into South Korea, Thailand with faster, more efficient data centers | Peter Cohen, RCR Wireless NewsAlibaba Cloud has announced plans to open new regional data centers in South Korea and Thailand. New server hardware from Alibaba Cloud improve data center…
IAR Systems Extends Functional Safety Offering for RISC-V with Build Tools for Linux | Tiera Oliver, Embedded Computing DesignIAR Systems announced that its build tools for RISC-V supporting deployment in Linux-based frameworks have been certified by TÜV SÜD for functional safety development. The…
Allwinner D1s/F133 RISC-V processor integrates 64MB DDR2 | Jean-Luc Aufranc, CNX SoftwareAllwinner D1s (aka F133) is a cost-down version of Allwinner D1 RISC-V processor introduced earlier this year together with a Linux capable development board, with…
IAR Systems extends functional safety offering for RISC-V with leading build tools for Linux | IAR SystemsIAR Build Tools for Linux for RISC-V now certified as a qualified tool for safety-related embedded development Uppsala, Sweden—October 25, 2021—IAR Systems®, the future-proof supplier…
A Lightweight Posit Processing Unit for RISC-V Processors in Deep Neural Network Applications | Marco Cococcioni, Federico Rossi, Emanuele Ruffaldi, and Saponara Sergio, IEEE Transactions on Emerging Topics in ComputingNowadays, two groundbreaking factors are emerging in neural networks. Firstly, there is the RISC-V open instruction set architecture (ISA) that allows a seamless implementation of…
Video: Accelerating Neural Networks using RISC-V and Open Standard Software | Charles Macfarlane, Codeplay SoftwareNeural Networks are foundational AI constructs for recognizing relationships in data requiring processing massive datasets in the form of tensors. Tensor processing is central to…
SiFive Envisions 128-Core RISC-V SoCs as Gap With x86 and Arm Closes | Anton Shilov, Tom’s HardwareSiFive emerged from stealth mode as a developer of small, low-power cores for microcontrollers in 2016. By late 2020, the company had a chip that…
ETH Zurich Team Unveils RISC-V-Based Snitch Processor, Boasts of Sixfold Performance Gains | Gareth Halfacree, Hackster.ioDesigned with two RISC-V ISA extensions, the Snitch chip is up to 6.45 times faster than comparable processors — and more efficient, too. A team…