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Imperas Announces Release of Simulator and Reference Models That Support Latest RISC-V Specifications | Imperas Software
Codasip Adopts Imperas for RISC-V Processor Verification Outlines vision for best-in-class RISC-V quality | Codasip
Branch Target Cache [BTC] (part 3) Managing a speculative subroutine call stack
See Western Digital’s SweRV Core family at the 2021 RISC-V Summit
Open Hardware: Skyrocketing Momentum & Global Adoption from Embedded to Enterprise | Calista Redmond, RISC-V International
FADU Technology Announces Speedy 14 GBps PCIe 5.0 SSD, up to 3.5 Million IOPS | Aaron Klotz, Tom’s Hardware
理研、創薬専用スパコン開発 「RISC-V」アーキテクチャ採用、10万原子の挙動再現 | [井上輝一，ITmedia
Compañía surcoreana anuncia una controladora PCIe 5.0 tipo RISC-V | Roberto Solé, Profesional Review
GCC Patches Pending For RISC-V’s Scalar Cryptography Extension | Michael Larabel, Phoronix
Video: ESP32-C3 Modular IoT board – OBJEX Link RISC-V | Salvatore Raccardi
OBJEX Link v1.6-C3 RISC-V | Salvatore Raccardi, Hackster.io
Video: Kneron 2021 semiconductor product launch | Kneron
Codasip Announces A71X RISC-V Application Core with Dual-Issue Capability
Segger and Codasip Announce Cooperation on RISC-V
SiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, Reuters
Life in a Formal Verification Lane | Shinavi Shah, SemiWiki.com
Video: RISC-V vs x86 – History and Key Differences Explained
SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs | Jim Salter, arsTechnica
Argonne, ORNL Award Codeplay Contract to Strengthen SYCL Support for AMD GPUs | HPCwire
SEGGER and Codasip Announce Cooperation on RISC-V
Imperas Announces Release of Simulator and Reference Models That Support Latest RISC-V Specifications | Imperas SoftwareImperas Software Ltd., a leader in RISC-V processor simulation and verification technology, today announced the latest product updates as a general release to all customers…
Codasip Adopts Imperas for RISC-V Processor Verification Outlines vision for best-in-class RISC-V quality | CodasipImperas Software Ltd., the leader in verification solutions for RISC-V, and Codasip, the leader in customizable RISC-V processor IP, today announced that Codasip has adopted…
Branch Target Cache [BTC] (part 3) Managing a speculative subroutine call stackThis is the third of an occasional series of articles on the VRoom!/RVoom RISC-V CPU. This week a shorter update, we’re going to talk about…
See Western Digital’s SweRV Core family at the 2021 RISC-V SummitRISC-V has been a very popular choice for embedded processor designs. Western Digital’s existing SweRV Core family is among the highest performance, area optimized embedded…
Open Hardware: Skyrocketing Momentum & Global Adoption from Embedded to Enterprise | Calista Redmond, RISC-V InternationalSee RISC-V International CEO Calista Redmond's keynote at Open Source Summit 2021 on Open Hardware: Skyrocketing Momentum and Global Adoption from Embedded to Enterprise. Watch…
FADU Technology Announces Speedy 14 GBps PCIe 5.0 SSD, up to 3.5 Million IOPS | Aaron Klotz, Tom’s HardwareNew SSD offers nearly twice the bandwidth of Gen 4 NVMe drives. Just as mainstream computers begin adopting PCIe Gen 5 support, FADU Technology has…
理研、創薬専用スパコン開発 「RISC-V」アーキテクチャ採用、10万原子の挙動再現 | [井上輝一，ITmedia理化学研究所は11月18日、水やタンパク質など分子の動きのシミュレーションに特化した専用計算機「MDGRAPE-4A」を開発したと発表した。1秒間に約1300兆回（1.3ペタフロップス）の計算が可能で、タンパク質と薬剤、水分子などを合わせた計10万個の原子の動きを、現実的な時間で解析できる。「創薬の可能性を広げるもの」と理研は期待を掛ける。 Read the full article.
Compañía surcoreana anuncia una controladora PCIe 5.0 tipo RISC-V | Roberto Solé, Profesional ReviewLa compañía coreana FADU habría desarrollado una controladora RISC-V para la interfaz PCIe 5.0. Habitualmente se utiliza la arquitectura ARM para las controladoras, pero esta…
GCC Patches Pending For RISC-V’s Scalar Cryptography Extension | Michael Larabel, PhoronixPatches were recently sent out that implement support for RISC-V's Scalar Cryptography Extension within the GNU Compiler Collection. The RISC-V Scalar Cryptography Extension work recently…
Video: ESP32-C3 Modular IoT board – OBJEX Link RISC-V | Salvatore RaccardiOBJEX Link RISC-V edition. This version of OBJEX Link "v1.6-C3" is based on the new ESP32-C3 which has a 32-bit single-core RISC-V processor. This version…
OBJEX Link v1.6-C3 RISC-V | Salvatore Raccardi, Hackster.ioThis version of OBJEX Link v1.6-C3 is based on the new ESP32-C3 which has a 32-bit single-core RISC-V processor - (Bluetooth 5.0 and WiFi 4).…
Video: Kneron 2021 semiconductor product launch | KneronWelcome to Kneron's 2021 semiconductor(KL530) product launch––join us in our explorations on the edge of next generation AI possibilities. Featured talks include "Future Automotives: The…
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Codasip Announces A71X RISC-V Application Core with Dual-Issue CapabilityMunich, Germany – June 22, 2021 – Codasip, the leading supplier of customizable RISC-V® processor IP, today announces a new major version of its most…
Segger and Codasip Announce Cooperation on RISC-VMonheim am Rhein & Munich, Germany – June 22nd, 2021 – SEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE…
SiFive aims to challenge Arm with new tech, pairs with Intel on effort | Stephen Nellis, ReutersJune 22 (Reuters) - SiFive Inc on Tuesday released a new computing chip design that aims to challenge Arm Ltd's dominance in smartphone chips and…
Life in a Formal Verification Lane | Shinavi Shah, SemiWiki.comThis summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working…
Video: RISC-V vs x86 – History and Key Differences Explainedx86 or x86-64 is the name of the architecture used by Intel and AMD to make their processors. RISC-V is a relatively new architecture that,…
SiFive’s brand-new P550 is one of the world’s fastest RISC-V CPUs | Jim Salter, arsTechnicaToday's RISC-V microcontrollers may lead to future RISC-V phones and laptops. Today, RISC-V CPU design company SiFive launched a new processor family with two core…
Argonne, ORNL Award Codeplay Contract to Strengthen SYCL Support for AMD GPUs | HPCwireLEMONT, Ill., OAK RIDGE, Tenn., and EDINBURGH, England, June 17, 2021 — Argonne National Laboratory (Argonne) in collaboration with Oak Ridge National Laboratory (ORNL), has…
SEGGER and Codasip Announce Cooperation on RISC-VSEGGER and Codasip announce that SEGGER’s J-Link debug probes and its Embedded Studio IDE fully support Codasip’s RISC-V processors, right out-of-the-box. SEGGER’s J-Link debug probe…
