With the high performance Alibaba T-Head XuanTie processor coming to market, we believe it will benefit the RISC-V industry to port RISCV to the Android…

Truechip, the Verification IP Specialist, today announced that it has introduced a Silicon IP to its product offering in addition to its existing Verification IP…

We covered Allwinner D1s RISC-V processor with 64MB built-in RAM a few days ago, and we’ve just found out about Xassette-Asterisk, an open-source hardware board…

With the recent advances in open source ASIC development tools such as Verible, it has become easier to automate tasks and boost developer productivity. The Verible linter…

This video explains the RV32I I-Type instructions. RISC-V is growing rapidly, follow this RISC-V video blog series to obtain knowledge about RISC-V processors, Instruction formats,…

MangoPi is prepping a tiny “MangoPi-MQ1” SBC with the new Allwinner F133-A (D1s), a spin-down of Allwinner’s D1 that adds 64MB RAM. Both SoCs use…

Supporting masking countermeasures for non-invasive side-channel security in instructions set architectures is a hard problem. Masked operations often have a large number of inputs and…

So far only called ‘Next Generation Core’ or Next-Gen, its official name, final design specs and availability will be unveiled early in December at the…

RISC-V CPU in TypeScript: Emulator Watch the full video. 

Codasip, a supplier of customisable RISC-V processor IP and tools, has announced further enhancements to its Studio processor design toolset. New features in Studio 9.1…

Based on the PULP Platform, this RISC-V chip could offer hundreds of thousands of hours of operation on a single battery charge. A team of…

Single-board computer startup MangoPi has shown off prototypes of a low-cost development board based on the recently-open sourced XuanTie C906 RISC-V core — and promises…

*RISC-V 32-bit Instruction Type Decode logic design in 120sec* Just imagine what all things you can do in RISC-V MYTH 5-day workshop. Many participants have…

Keynote Session: Hypervisor Extensions in RISC-V - Robert Eshleman, Vates SAS This talk presents the virtualization capabilities offered by the RISC-V Hypervisor ISA extension (H…

Monheim am Rhein, Germany – May 31, 2021 -- The SEGGER emRun runtime library is available as part of the recently announced SiFive 21G1 release. SiFive’s…

The RISC-V architecture, which is in direct competition with ARM, is making more news headlines recently. So how do RISC-V and ARM differ, what products…

Alibaba’s cloud computing unit is making its Apsara operating system compatible with processors based on Arm, x86, RISC-V, among other architectures, the company announced at a conference on…

This talk is on the technical paper presented at DVCon 2021. Abstract: The open RISC-V instruction set architecture is gaining traction with both semiconductor vendors…

It’s a certain kind of itch that drives people to voluntarily build their own CPU. We start thinking about the papered-over gap in our understanding, the…

SEMICONDUCTOR SCALING HAS FUNDAMENTALLY CHANGED For about fifty years, IC designers have been relying on different types of semiconductor scaling to achieve gains in performance.…

Last month, we wrote about Allwinner D1 SBC & processor that promised to offer a relatively low-cost RISC-V Linux solution. We were not given a name at…

At first glance, the HiFive Unmatched from SiFive looks like just another mini ITX computer motherboard. But rather than an x86 chip, this system is powered by…

The 64bit RISC-V Raspberry Pi alternative we wrote about last month has turned up again, this time on Indiegogo, with a new name. The Nezha board, named after a protective…

May 21, 2021 -- Your next MCU needs to be more than just smart. It needs to be power-efficient, have ample memory, and industrial-grade security.…