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AheadComputing Secures $21.5M to Drive RISC-V Innovation for AI and Cloud
Checking Out The RISC V HiFive P550 from SiFive!
Why RISC-V is a viable option for safety-critical applications
TestRIG – Randomized Testing of RISC-V CPUs
Cloud-based RISC-V evaluation platform for sustainable compute
Groundbreaking Formal Verification Further Enhances the Quality of CHERIoT-Ibex
First RISC-V mainboard for modular laptop
VyperCore launches VyperLab, an evaluation platform to showcase its innovative compute accelerator technology
Nvidia RTX 5090 Graphics Card Review — Get Neural Or Get Left Behind
Accelerating RISC-V development with Tessent UltraSight-V
Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional Safety
Tiny RISC-V chip for the digital product passport (DPP)
Community Growth in India through Vegathon Events | RISC-V International
RISC-V’s Worldwide Expansion and Andes Technology’s Contribution
Accelerate Your Success by Joining RISC-V Membership
Raising RISC-V processor quality with formal verification
Adapting OpenTitan for open source FPGA prototyping and tooling development
[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT Podcast
Announcing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | Tenstorrent
A dual-core TEE security solution based on E902
Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGA
Catch up with the best of the RISC-V booth from Embedded World 2023Top Ten Fallacies About RISC-V
Tiempo Secure brings additional security features to the RISC-V ecosystem
Community Growth in India through Vegathon Events | RISC-V InternationalRISC-V’s Worldwide Expansion and Andes Technology’s ContributionAccelerate Your Success by Joining RISC-V MembershipRaising RISC-V processor quality with formal verificationAdapting OpenTitan for open source FPGA prototyping and tooling development[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT PodcastAnnouncing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | TenstorrentA dual-core TEE security solution based on E902Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGACatch up with the best of the RISC-V booth from Embedded World 2023Top Ten Fallacies About RISC-VTiempo Secure brings additional security features to the RISC-V ecosystem
MIPS releases RISC-V CPU for autonomous vehicles
The Convergence of Functional with Safety, Security and PPA Verification
Highlights from the RISC-V Summit 2024
Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
Interview with RISC-V International: High-Performance Chips, AI, Ecosystem Fragmentation, and The Future
RISC-V Oozes Confidence with RVA23 Profile Ratification
4 Highlights From the RISC-V Summit North America
DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
RISC-V User-Space Pointer Masking Appears Ready For Linux 6.13Denso seals Quadric deal for RISC-V AI coreRISC-V CPU demoed with RX 7900 XTX GPU in Debian Linux — AMD flagship GPU paired with Milk-V Megrez board and SiFive P550 cores
Codasip Unveils L730 Automotive-Grade Embedded RISC-V Core
AheadComputing Secures $21.5M to Drive RISC-V Innovation for AI and CloudPORTLAND, Ore., Feb. 19, 2025 — AheadComputing today announced it has secured $21.5 million in seed funding to rapidly develop and commercialize its advanced microprocessor architecture designed…
Checking Out The RISC V HiFive P550 from SiFive!Ever wanted to get in on the ground floor of something really cool? Wendell shows you how you can get involved with RISC V development…
Why RISC-V is a viable option for safety-critical applicationsAn intro to RISC-V As safety-critical systems become increasingly complex, the choice of processor architecture plays an important role in ensuring functional safety and system…
TestRIG – Randomized Testing of RISC-V CPUsTestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in…
Cloud-based RISC-V evaluation platform for sustainable computeUK startup VyperCore is launching a cloud-based evaluation platform for its sustainable RISC-V accelerator chip and chiplet. The VyperLab platform runs on an FPGA in…
Groundbreaking Formal Verification Further Enhances the Quality of CHERIoT-IbexCollaboration milestone addresses key pain points of typical design verification (DV) approaches, improving confidence while reducing cost, time, and resource spend CAMBRIDGE, England – 10th February, 2025 – lowRISC C.I.C.,…
First RISC-V mainboard for modular laptopA RISC-V processor board is available for the first time for the modular Framework laptop as a development system. The DC-Roma mainboard from DeepComputing can…
VyperCore launches VyperLab, an evaluation platform to showcase its innovative compute accelerator technologyCambridge, United Kingdom – 11 February 2025 – VyperCore, the pioneering high performance processor company, has launched VyperLab, a new cloud-based evaluation platform for its groundbreaking…
Nvidia RTX 5090 Graphics Card Review — Get Neural Or Get Left BehindWhen Nvidia first announced the RTX 5000 series of graphics cards at CES 2025, it was clear that the company would be leaning even further…
Accelerating RISC-V development with Tessent UltraSight-VBy: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early…
Andes Technology D45-SE Processor Achieves ISO 26262 ASIL-D Certification for Functional SafetyHSINCHU, TAIWAN, Jan. 23, 2025 (GLOBE NEWSWIRE) -- Andes Technology, a leading provider of RISC-V processor cores, today announced that its D45-SE processor has successfully…
Tiny RISC-V chip for the digital product passport (DPP)The RISC-V microcontroller NXP EdgeLock A30 is an "authenticator" that stores digital information and protects it from unauthorized modification. Among other things, the A30 is…
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Community Growth in India through Vegathon Events | RISC-V InternationalThirty hours! That’s how long some of the recent VEGA Processors hackathons, VEGATHON, have lasted. At a recent hackathon local RISC-V enthusiasts used the RISC-V-based…
RISC-V’s Worldwide Expansion and Andes Technology’s ContributionA Q&A with Andes’ Board of Directors’ Advisor Charlie Cheng, Managing Director of Polyhedron. What is Andes Technology and how has it grown in…
Accelerate Your Success by Joining RISC-V MembershipRISC-V is truly inevitable. The forecasts and growth of RISC-V across the industry are growing at an unprecedented rate. As the demand and opportunity for…
Raising RISC-V processor quality with formal verificationBy Laurent Arditi, Codasip During the development of a mid-range complexity RISC-V processor, you can discover hundreds or even thousands of bugs. As you introduce…
Adapting OpenTitan for open source FPGA prototyping and tooling developmentAntmicro’s projects often involve helping companies address their specific processing, security and other needs through designing and prototyping ASIC solutions with open source tools and…
[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT PodcastAbout this Episode In season 3 episode 6 connect with Ashish Darbari – Founder & CEO at Axiomise to discover how formal verification is being…
Announcing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | TenstorrentTenstorrent, a leading AI semiconductor company, is proud to announce its upcoming RISC-V event in India. The event will be an excellent opportunity to immerse…
A dual-core TEE security solution based on E902Jiacheng Yang, Yahui Teng, Bingquan Huang Guangdong University of Technology In the China Postgraduate IC Innovation Competition this August, T-Head sponsored the design challenge: Building…
Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGACanonical published the optimized Ubuntu release for the first RISC-V based System-on-Chip (SoC) field-programmable gate array (FPGA)—our PolarFire® SoC FPGA Icicle Kit, expanding support for…
Catch up with the best of the RISC-V booth from Embedded World 2023Embedded World 2023 showed great momentum for RISC-V. Across the show, our members were demonstrating new technologies and developing new relationships, bringing RISC-V to a…
Top Ten Fallacies About RISC-VDavid Patterson, Pardee Professor of Computer Science, Emeritus at UC Berkeley and Vice Chair of the RISC-V International Board of Directors Following the Fallacies and…
Tiempo Secure brings additional security features to the RISC-V ecosystemThe IoT world is especially exposed to cyberattacks. As of now, industry leaders are demonstrating the interest of Secure Elements and Secure Enclaves for reaching…
No recent posts listed
Community Growth in India through Vegathon Events | RISC-V InternationalThirty hours! That’s how long some of the recent VEGA Processors hackathons, VEGATHON, have lasted. At a recent hackathon local RISC-V enthusiasts used the RISC-V-based…
RISC-V’s Worldwide Expansion and Andes Technology’s ContributionA Q&A with Andes’ Board of Directors’ Advisor Charlie Cheng, Managing Director of Polyhedron. What is Andes Technology and how has it grown in…
Accelerate Your Success by Joining RISC-V MembershipRISC-V is truly inevitable. The forecasts and growth of RISC-V across the industry are growing at an unprecedented rate. As the demand and opportunity for…
Raising RISC-V processor quality with formal verificationBy Laurent Arditi, Codasip During the development of a mid-range complexity RISC-V processor, you can discover hundreds or even thousands of bugs. As you introduce…
Adapting OpenTitan for open source FPGA prototyping and tooling developmentAntmicro’s projects often involve helping companies address their specific processing, security and other needs through designing and prototyping ASIC solutions with open source tools and…
[PODCAST] Making Formal Verification the New Normal in IoT with Ashish Darbari – Founder, Axiomise | The IoT PodcastAbout this Episode In season 3 episode 6 connect with Ashish Darbari – Founder & CEO at Axiomise to discover how formal verification is being…
Announcing the Nerds Talking to Nerds About RISC-V event hosted by Tenstorrent | TenstorrentTenstorrent, a leading AI semiconductor company, is proud to announce its upcoming RISC-V event in India. The event will be an excellent opportunity to immerse…
A dual-core TEE security solution based on E902Jiacheng Yang, Yahui Teng, Bingquan Huang Guangdong University of Technology In the China Postgraduate IC Innovation Competition this August, T-Head sponsored the design challenge: Building…
Canonical Enables Ubuntu on Microchip’s PolarFire® SoC FPGACanonical published the optimized Ubuntu release for the first RISC-V based System-on-Chip (SoC) field-programmable gate array (FPGA)—our PolarFire® SoC FPGA Icicle Kit, expanding support for…
Catch up with the best of the RISC-V booth from Embedded World 2023Embedded World 2023 showed great momentum for RISC-V. Across the show, our members were demonstrating new technologies and developing new relationships, bringing RISC-V to a…
Top Ten Fallacies About RISC-VDavid Patterson, Pardee Professor of Computer Science, Emeritus at UC Berkeley and Vice Chair of the RISC-V International Board of Directors Following the Fallacies and…
Tiempo Secure brings additional security features to the RISC-V ecosystemThe IoT world is especially exposed to cyberattacks. As of now, industry leaders are demonstrating the interest of Secure Elements and Secure Enclaves for reaching…
MIPS releases RISC-V CPU for autonomous vehiclesMIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications. The San Jose, California-based company, which focuses…
The Convergence of Functional with Safety, Security and PPA VerificationFormal For All! “Do I need a PhD to use formal verification?” “Can formal methods really scale?” “Is it too difficult to write formal properties…
Highlights from the RISC-V Summit 2024What you’ll learn: The state of RISC-V, including new RISC-V announcements. A look at some good video presentations at the 2024 RISC-V Summit. RISC-V trends…
Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI InferenceSan Jose, CA — Oct. 22, 2024 — Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…
Interview with RISC-V International: High-Performance Chips, AI, Ecosystem Fragmentation, and The FutureRISC-V is an industry standard instruction set architecture (ISA) born in UC Berkeley. RISC-V is the fifth iteration in the lineage of historic RISC processors.…
RISC-V Oozes Confidence with RVA23 Profile RatificationLast week’s RISC-V Summit in Santa Clara, Calif., had an air of confidence that we have not seen at previous summits. There was much for…
4 Highlights From the RISC-V Summit North AmericaIn this roundup, we discuss several announcements from last week's summit pushing RISC-V adoption and processing power. Four companies, including Andes Technology, RISC-V International, Arteris,…
DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu DesktopSan Jose, CA — Oct 22, 2024 — DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power…
RISC-V User-Space Pointer Masking Appears Ready For Linux 6.13It looks like the upcoming Linux 6.13 cycle will be adding RISC-V support for user-space pointer masking and tagged address ABI. RISC-V pointer masking can be used…
Denso seals Quadric deal for RISC-V AI coreLeading Japanese automotive supplier Denso is expanding its semiconductor business through a development license agreement for a Neural Processing Unit (NPU) AI core from Quadric…
RISC-V CPU demoed with RX 7900 XTX GPU in Debian Linux — AMD flagship GPU paired with Milk-V Megrez board and SiFive P550 coresRISC-V firm Milk-V demonstrated that it can get AMD’s RX 7900 XTX graphics card to work on one of its RISC-V boards. The PC shown in the…
Codasip Unveils L730 Automotive-Grade Embedded RISC-V CoreMUNICH, Germany, Oct 28, 2024 – Codasip has announced its new L730 core. Codasip L730 is a high-quality, high-performance embedded core that meets automotive safety and security…