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Q&A with RISC-V Ambassador Wei Fu on the Growth and Future of RISC-V

By June 1, 2020September 30th, 2020No Comments

The inaugural group of RISC-V Ambassadors was announced in March 2020, consisting of an incredible group of engineers, developers and influencers that have actively contributed to the RISC-V community. The RISC-V Ambassadors are passionate about growing and engaging the RISC-V community by: promoting RISC-V projects and technology; educating people on the RISC-V mission and technical aspects; and helping to drive RISC-V member participation and community growth. To learn more about the program, we spoke with RISC-V Ambassador Wei Fu who is a senior software engineer at Red Hat.
1. How did you first become involved with the RISC-V ecosystem?
I first became aware of RISC-V four years ago, and ever since, I’ve become very passionate about the technology and its potential to disrupt the industry. In 2017 at the RISC-V Day in Tokyo, I was fortunate to have the opportunity to present on my findings on Fedora and RISC-V. Since then I’ve dedicated my time to growing and engaging with the RISC-V community, particularly spreading awareness around the benefits of RISC-V and Fedora. What interests me the most about RISC-V is that the instruction set architecture (ISA) is completely open and engineers have the opportunity to design chips more freely, while also benefiting from the open source software and hardware ecosystem.
2. Why are you excited about RISC-V?
Compared to proprietary cores, RISC-V brings many promising advantages to the table for companies looking to design processor cores for newer workloads, such as artificial intelligence or machine learning, because the ISA is simple, efficient, and extensible and has no constraints. I’m a true believer that RISC-V will bring revolutionary change to the industry and more companies will leverage the ISA moving forward.
3. How do you think RISC-V is changing the industry?
RISC-V is a new architecture that is changing how industry professionals think of and view computing design. The ISA is available under open, free and non-restrictive licenses, and it already has widespread industry support from chip and device makers; plus RISC-V is designed to be freely extensible and customizable to fit any market. Simply put, RISC-V allows chip designers to start with a new clean sheet of paper and have more freedom to map out and optimize their SoC designs for newer computing demands and workloads.
4. What are your goals as a RISC-V Ambassador?
As the first Chinese RISC-V Ambassador, my goal is to spread awareness of the ISA’s values and benefits in China, and also help our Chinese member companies contribute to our global ecosystem. Since I have the privilege of working at Red Hat, I am also responsible for spreading awareness of Red Hat’s solutions to the ecosystem and participating in our dedicated technical committees to help create new RISC-V standards, extensions and tools. Currently, I’m focused on developing advancements and standards for Linux Distro on RV64 and Fedora on RV32GC.
5. How would you like to see the RISC-V ecosystem evolve over the next few years?
The future of operating systems on RISC-V is promising, and I’m excited to see our community contribute new advances to the real-time operating system (RTOS) and Fedora ecosystems.
Specifically for Fedora, developers are quickly witnessing the value RISC-V offers. I envision it will become either the primary or secondary architecture used moving forward to accelerate the platform for hardware, cloud, and containers, and enable software developers and its community members to build tailored solutions for their users. Many of us are working on building the latest Fedora packages for RISC-V on a large number of emulators and a small number of hardware systems. For example, see below for a few webpages regarding our latest package and system build for Koji servers. We are also working on a new Koji system in China for RV32 and RV64, and bootstrapping Fedora on RV32.

Additionally, the RISC-V community is continuing to invest its time and energy in building new advancements for the RTOS ecosystem, so I foresee RTOS on RISC-V becoming more mainstream. Furthermore, in the next few years, our community will develop RISC-V cores that will be ready to move beyond the accelerator and microcontroller domain to be incorporated into full-fledged RISC-V CPUs for desktops and servers.
6. (Optional) Are you working on any personal RISC-V projects?
Yes, I’m currently working on a few RISC-V projects of my own. Right now, I’m looking into how RISC-V can offer advancements for RTOS such as RT-Thread and Zephyr and Fedora bootstrap on RV32. I’m planning to share my contributions with the wider ecosystem soon, so stay tuned!
Visit here to learn more about the RISC-V Ambassador Program and apply to become an Ambassador.

About the Author

Wei Fu is one of the first RISC-V Ambassadors and a senior software engineer at Red Hat. Fu has an extensive background in developing embedded and enterprise systems on Linux and has experience with Linux kernel, BSP, system porting development and testing. He is currently studying everything there is to know about RISC-V, Fedora, GRUB, UEFI, ACPI and continuously reads up on Linux Servers, especially SBSA and SBBR. Additionally, Wei is also learning as much as he can regarding RTOS (RT-Thread, Zephyr, FreeRTOS), OpenWRT, IoT (hardware and software architecture), Arduino, drones, Bluetooth/BLE, Wi-Fi, security and encryption, and other OSS projects.

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