Abhishek Jadhav shares the sessions they are looking forward to at the RISC-V Global Forum, an 18-hour event on September 3. Click to register.
There is an increase in demand for processors that will address concerns related to security, graphics, high-performance computing, and artificial intelligence. All the popular proprietary instruction set architectures (ISA) currently available have restricted the growth in many ways. This year has been incredibly good for open source RISC-V Community with exceptional contributions. During this COVID-19 pandemic, SiFive has contributed its E21 Standard Embedded Processor Core for use in devices that will help in controlling the pandemic and minimizing the impact of the disease.
Many undergraduate and graduate students (academia) are taking up RISC-V ISA for high-end projects. As there is an increase in demand for open source ISA, countries like India have adopted RISC-V as the national ISA. Calista Redmond (CEO, RISC-V International) and Stefan Wallentowitz (Professor, Munich University of Applied Sciences) will be initiating the discussion on ‘RISC-V in Academia and Education’ at the RISC-V Global Forum. There is one such undergraduate students’ group from China that will be presenting on ‘Nutshell: A Linux-Compatible RISC-V Processor’. This is an in-order Linux-Compatible RISC-V processor that supports RV64IMAC instruction extension and SV39 virtual-memory system. Another contribution that will come from academia is from IIT, Madras (India) on ‘ProtoCPU: Modelling an in-order RISC-V Core in gem5’, which fulfills the workflow of product development process by aiding in the simulation of an in-order RISC-V processor.
Open ISA like RISC-V has enabled a complete open SW/HW stack/ecosystem for the world. European Processor Initiative (EPI) will be presenting ‘EPI, the European approach for Exascale ages: The road toward sovereignty’. EPI is developing the processor that will empower the European Exascale machines, and will lay the foundations of the European Sovereignty for high-performance and low-power processing units based in RISC-V, the Opensource ISA. Also, one session on ‘Noel-V: A New High-Performance RISC-V Processor Family’ by Cobham Gaisler AB will introduce its open source high-performance Noel-V processors with fault tolerance, L2-cache and a pipelined FPU, which can be licensed commercially.
With increasing complexity of processors, verification consumes the highest development time in any project. Today, cloud-based verification has provided scalability, elastic storage availability that has led to many developments. ‘Cloud-based Verification of Open Source RISC-V Cores’ will be discussed by Codasip and Metrics Design Automation. More on verification, there will be ‘CORE-V Verification Test Bench – Commercial Quality Verification of Open-Source RISC-V Cores’ by Metrics Design Automation, Imperas Software and OpenHW. The CORE-V Verification Test Bench is an open-source ‘step & compare’ System Verilog / UVM environment built by the OpenHW Group ecosystem leveraging the Imperas RISC-V Golden Reference Model and the Metrics Cloud-based EDA Platform.
At the end of the Global Forum there will be a keynote address on ‘The First Decade of RISC-V: A Worldwide Phenomenon’ by David Patterson (Vice Chair, RISC-V International).
Stay tuned for 18 hours schedule of RISC-V Global Forum, save the date September 3, 2020!