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Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies Inc
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalEverything RISC-V at the Design Automation Conference! | RISC-V International
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba Cloud
PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | Microchip
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep Computing
SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, Syntacore
Democratizing Chiplet-Based Processor Design | Ventana Micro Systems
RISC-V Vector Processing is Taking Off | SiFive
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies
Overtake the Competition in Automotive Design with RISC-V Innovations | CodasipRISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International
RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC Workloads
RISC-V RV32I RTL Architecture | Maven Silicon
The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10
Antmicro Open Source Portal launched
New Open Source Contributor Model: RISC-V Development Partners
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!
RISC-V RV32I Instructions Format | Maven Silicon
seL4 on RISC-V Verified to Binary Code
The world’s first DSP based on RISC-V ISA is about to be mass-produced
RISC-V Developer Boards to drive innovation
Bugs: A verification engineer’s dream, a designer’s nightmare
RISC-V Application to Machine Language | Maven Silicon
RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC WorkloadsRISC-V RV32I RTL Architecture | Maven SiliconThe Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10Antmicro Open Source Portal launchedNew Open Source Contributor Model: RISC-V Development PartnersComing June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!RISC-V RV32I Instructions Format | Maven SiliconseL4 on RISC-V Verified to Binary CodeThe world’s first DSP based on RISC-V ISA is about to be mass-producedRISC-V Developer Boards to drive innovationBugs: A verification engineer’s dream, a designer’s nightmareRISC-V Application to Machine Language | Maven Silicon
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies IncMachine learning (ML) recommendation workloads have demanding performance and memory requirements and, to date, have largely been run on servers with x86 processors. To accelerate…
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalIn Spring 2022, various mentorship projects were offered by RISC-V International on the LFX platform of the Linux Foundation. I got selected for one of…
Everything RISC-V at the Design Automation Conference! | RISC-V InternationalThe Design Automation Conference is here and we're thrilled to share look at all the RISC-V happenings during the show. If you are interested in…
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudLast year Alibaba T-Head reported that the basic features of Android had been ported onto RISC-V-based Xuantie cores. Since then more effort has been spent…
PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | MicrochipOperational Technology (OT) and Transportation and Industrial Control Systems (ICS) are often forced to make concessions regarding security and updates to deliver critical functionality without…
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep ComputingROMA development platform features forthcoming quad-core RISC-V processor for fastest, seamless RISC-V software development experience. DeepComputing and Xcalibyte today opened pre-orders for the industry’s first…
SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, SyntacoreYADRO and Syntacore hosted the first ever engineering hackathon for students in Russia. The event was organized in association with National Research University of Electronic…
Democratizing Chiplet-Based Processor Design | Ventana Micro SystemsBy Bob Wheeler, Principal Analyst, The Linley Group Chiplet-based designs promise reduced development costs and faster time to market, but they’ve been exclusive to large…
RISC-V Vector Processing is Taking Off | SiFiveThe RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector…
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves TechnologiesLocated in the micro-and nano-electronics hotspot of Grenoble, GreenWaves is a fabless semiconductor startup that designs and brings to market advanced ultra-low-power AI and DSP…
Overtake the Competition in Automotive Design with RISC-V Innovations | CodasipIn conversation with Jamie Broome, Codasip VP of Automotive Jamie Broome recently joined Codasip as VP Automotive with more than 20 years of semiconductor…
RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V InternationalEfficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline…
No recent posts listed
RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC WorkloadsRISC-V was first deployed as a microcontroller or embedded processor. However, in the future, the RISC-V ISA can also power the most powerful computers as…
RISC-V RV32I RTL Architecture | Maven SiliconThis video explains the RTL architecture of an RV32I RISC-V processor. Also, it shows how we can create the RISC-V RTL using basic building blocks…
The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10“RISC-V and Zephyr were both designed to drive innovation in the hardware space with open source technologies that are accessible to everyone,” said Mark Himelstein,…
Antmicro Open Source Portal launchedAntmicro was founded on the belief that open source can dramatically accelerate technological progress by enabling collaboration, transparency and freedom to customize, improve and combine…
New Open Source Contributor Model: RISC-V Development PartnersThe growth of RISC-V is built on the collaborative efforts of the individuals and organizations in the technical community. Our continued progress relies on the…
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to…
RISC-V RV32I Instructions Format | Maven SiliconThis video explains all RV 32I Instruction formats, R, I, S, B, J, and U types, and how it simplifies the instruction decoder logic. Follow…
seL4 on RISC-V Verified to Binary CodeAuthor: Gernot Heiser, seL4 FoundationIn June 2020 we announced that the seL4 microkernel, the world’s first operating system (OS) kernel with a machine-checked proof of…
The world’s first DSP based on RISC-V ISA is about to be mass-producedRISC-V, the "youngest" ISA (Instruction Set Architecture), which was born in year 2010, has attracted many giant supporters, such as Google, Qualcomm, Western Digital, Alibaba,…
RISC-V Developer Boards to drive innovationWe are at an incredible inflection point for RISC-V. We are making history and we want you to be a part of it! RISC-V is…
Bugs: A verification engineer’s dream, a designer’s nightmareThis blog was originally published on the Axiomise website. Read the original blog. Who wants to have bug escapes? Nobody. Who wants to have bugs…
RISC-V Application to Machine Language | Maven SiliconRISC-V Application to Machine Language March 17, 2021 Sivakumar P R This video explains how a RISC-V processor executes all the software applications written in the…
No recent posts listed
RISC-V SIG-HPC Enabling RISC-V in HPC, Supercomputers to the Edge, and Emerging AI/ML/DL HPC WorkloadsRISC-V was first deployed as a microcontroller or embedded processor. However, in the future, the RISC-V ISA can also power the most powerful computers as…
RISC-V RV32I RTL Architecture | Maven SiliconThis video explains the RTL architecture of an RV32I RISC-V processor. Also, it shows how we can create the RISC-V RTL using basic building blocks…
The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10“RISC-V and Zephyr were both designed to drive innovation in the hardware space with open source technologies that are accessible to everyone,” said Mark Himelstein,…
Antmicro Open Source Portal launchedAntmicro was founded on the belief that open source can dramatically accelerate technological progress by enabling collaboration, transparency and freedom to customize, improve and combine…
New Open Source Contributor Model: RISC-V Development PartnersThe growth of RISC-V is built on the collaborative efforts of the individuals and organizations in the technical community. Our continued progress relies on the…
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to…
RISC-V RV32I Instructions Format | Maven SiliconThis video explains all RV 32I Instruction formats, R, I, S, B, J, and U types, and how it simplifies the instruction decoder logic. Follow…
seL4 on RISC-V Verified to Binary CodeAuthor: Gernot Heiser, seL4 FoundationIn June 2020 we announced that the seL4 microkernel, the world’s first operating system (OS) kernel with a machine-checked proof of…
The world’s first DSP based on RISC-V ISA is about to be mass-producedRISC-V, the "youngest" ISA (Instruction Set Architecture), which was born in year 2010, has attracted many giant supporters, such as Google, Qualcomm, Western Digital, Alibaba,…
RISC-V Developer Boards to drive innovationWe are at an incredible inflection point for RISC-V. We are making history and we want you to be a part of it! RISC-V is…
Bugs: A verification engineer’s dream, a designer’s nightmareThis blog was originally published on the Axiomise website. Read the original blog. Who wants to have bug escapes? Nobody. Who wants to have bugs…
RISC-V Application to Machine Language | Maven SiliconRISC-V Application to Machine Language March 17, 2021 Sivakumar P R This video explains how a RISC-V processor executes all the software applications written in the…