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Hot Chips and Even Hotter Connections: RISC-V is Everywhere!
Wine Down Friday with RISC-V’s Calista Redmond
Trailblazers: Board of Directors Software Award Winners 2024
RISC-V Builds the Backbone of Three New Consumer Devices
STMicroelectronics Joins Quintauris as Sixth Shareholder
Orange Pi Embraces RISC-V with the Raspberry Pi-Like Orange Pi RV Single-Board ComputeRISC-V Enables Performant and Flexible AI and ML Compute
SiFive and Arkmicro Accelerate RISC-V Adoption in Automotive Electronics with SiFive’s Automotive IP for the High-end SoC MarketJesse Taube Gets Linux Up and Running on the Raspberry Pi RP2350’s Hazard3 RISC-V Cores
RISC-V International N-Trace TG Milestone
Resiltech To Develop Test Libraries for Andes ASIL-D RISC-V Processor IP
Exploring the Amazing RISC-V Summit China 2024
RISC-V RV32I RTL Architecture | Maven Silicon
The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10
Antmicro Open Source Portal launched
New Open Source Contributor Model: RISC-V Development Partners
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!
RISC-V RV32I Instructions Format | Maven Silicon
seL4 on RISC-V Verified to Binary Code
The world’s first DSP based on RISC-V ISA is about to be mass-produced
RISC-V Developer Boards to drive innovation
Bugs: A verification engineer’s dream, a designer’s nightmare
RISC-V Application to Machine Language | Maven Silicon
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project
RISC-V RV32I RTL Architecture | Maven SiliconThe Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10Antmicro Open Source Portal launchedNew Open Source Contributor Model: RISC-V Development PartnersComing June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!RISC-V RV32I Instructions Format | Maven SiliconseL4 on RISC-V Verified to Binary CodeThe world’s first DSP based on RISC-V ISA is about to be mass-producedRISC-V Developer Boards to drive innovationBugs: A verification engineer’s dream, a designer’s nightmareRISC-V Application to Machine Language | Maven SiliconBringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT project
Ashling announces RiscFree™ C/C++ SDK support for Renesas’s RISC-V-based R9AG021 MCUsIndustry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical ActivitiesRISC-V International Names Andrea Gallo as VP, Technology
Ventana CEO to Deliver a Keynote at RISC-V Summit Europe
[VIDEO] Road to testing applications on RISC-V with QEMU and Fedora – DevConf.CZ 2024
Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification CoverageCompanies Rally RISC-V Support for AI and HPC Applications
[VIDEO] M1: RISC-V Overview | The Ultimate Guide to RISC-V Architecture
Follow the Leader – Synopsys Provides Broad Support for Processor EcosystemsSipeed Univels the Lichee Book 4A, a Notebook for the “RISC-V Explorer”
Functional safety static analysis tool for RISC-V
Hot Chips and Even Hotter Connections: RISC-V is Everywhere!The weather might have been scorching, but the networking at Hot Chips was on fire! RISC-V was front and center, showcasing member boards, and fielding…
Wine Down Friday with RISC-V’s Calista RedmondIn this episode of Wine Down Friday, we are thrilled to welcome Calista Redmond, CEO of RISC-V International. Calista shares her journey from IBM to…
Trailblazers: Board of Directors Software Award Winners 2024Four software leaders were honored at RISC-V Summit Europe 2024 for their remarkable contributions to the RISC-V Community. Let’s celebrate their induction into the RISC-V…
RISC-V Builds the Backbone of Three New Consumer DevicesRISC-V, the open-standard ISA, has inspired a host of innovative designs in tablets, cameras, and laptops. In the past few years, RISC-V has transitioned from…
STMicroelectronics Joins Quintauris as Sixth ShareholderThe semiconductor manufacturer is the latest organisation to join other industry players exploring the potential of RISC-V architecture Munich, Germany – August 29, 2024 –…
Orange Pi Embraces RISC-V with the Raspberry Pi-Like Orange Pi RV Single-Board ComputeJoining the likes of PINE64, Geniatech, and Milk-V, Orange Pi announces a Raspberry Pi-like SBC built atop the StarFive JH7110. Single-board computer specialist Orange Pi…
RISC-V Enables Performant and Flexible AI and ML ComputeThe emergence of Artificial Intelligence (AI) and Machine Learning (ML) is one of the most significant computing trends in recent history. According to research, by…
SiFive and Arkmicro Accelerate RISC-V Adoption in Automotive Electronics with SiFive’s Automotive IP for the High-end SoC MarketSanta Clara, Calif. - September 2, 2024 — Today SiFive, Inc. announced that it has licensed its SiFive Automotive RISC-V IP cores to Arkmicro Technologies (Shenzhen), accelerating the…
Jesse Taube Gets Linux Up and Running on the Raspberry Pi RP2350’s Hazard3 RISC-V CoresDeveloper Jesse Taube has become the first to successfully boot a minimal Linux distribution on the Raspberry Pi Pico 2's RP2350 microcontroller — taking advantage…
RISC-V International N-Trace TG MilestoneThe market is experiencing a major shift to the RISC-V ISA and MIPS is helping to fuel this transition with high performance RISC-V cores, including…
Resiltech To Develop Test Libraries for Andes ASIL-D RISC-V Processor IPAndes Technology in Taiwan has confirmed details of its deal with Italian software provider Resiltech for Software Test Libraries (STL) for automotive-grade RISC-V processor IP.…
Exploring the Amazing RISC-V Summit China 2024By: The RISC-V Summit China Team The 4th RISC-V Summit China 2024 was successfully held in Hangzhou from August 21st to 23rd. This summit brought…
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RISC-V RV32I RTL Architecture | Maven SiliconThis video explains the RTL architecture of an RV32I RISC-V processor. Also, it shows how we can create the RISC-V RTL using basic building blocks…
The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10“RISC-V and Zephyr were both designed to drive innovation in the hardware space with open source technologies that are accessible to everyone,” said Mark Himelstein,…
Antmicro Open Source Portal launchedAntmicro was founded on the belief that open source can dramatically accelerate technological progress by enabling collaboration, transparency and freedom to customize, improve and combine…
New Open Source Contributor Model: RISC-V Development PartnersThe growth of RISC-V is built on the collaborative efforts of the individuals and organizations in the technical community. Our continued progress relies on the…
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to…
RISC-V RV32I Instructions Format | Maven SiliconThis video explains all RV 32I Instruction formats, R, I, S, B, J, and U types, and how it simplifies the instruction decoder logic. Follow…
seL4 on RISC-V Verified to Binary CodeAuthor: Gernot Heiser, seL4 FoundationIn June 2020 we announced that the seL4 microkernel, the world’s first operating system (OS) kernel with a machine-checked proof of…
The world’s first DSP based on RISC-V ISA is about to be mass-producedRISC-V, the "youngest" ISA (Instruction Set Architecture), which was born in year 2010, has attracted many giant supporters, such as Google, Qualcomm, Western Digital, Alibaba,…
RISC-V Developer Boards to drive innovationWe are at an incredible inflection point for RISC-V. We are making history and we want you to be a part of it! RISC-V is…
Bugs: A verification engineer’s dream, a designer’s nightmareThis blog was originally published on the Axiomise website. Read the original blog. Who wants to have bug escapes? Nobody. Who wants to have bugs…
RISC-V Application to Machine Language | Maven SiliconRISC-V Application to Machine Language March 17, 2021 Sivakumar P R This video explains how a RISC-V processor executes all the software applications written in the…
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
No recent posts listed
RISC-V RV32I RTL Architecture | Maven SiliconThis video explains the RTL architecture of an RV32I RISC-V processor. Also, it shows how we can create the RISC-V RTL using basic building blocks…
The Zephyr Project Celebrates 5th Anniversary with new members and inaugural Zephyr Developer Summit on June 8-10“RISC-V and Zephyr were both designed to drive innovation in the hardware space with open source technologies that are accessible to everyone,” said Mark Himelstein,…
Antmicro Open Source Portal launchedAntmicro was founded on the belief that open source can dramatically accelerate technological progress by enabling collaboration, transparency and freedom to customize, improve and combine…
New Open Source Contributor Model: RISC-V Development PartnersThe growth of RISC-V is built on the collaborative efforts of the individuals and organizations in the technical community. Our continued progress relies on the…
Coming June 2 – RISC-V Developer Tools and Tool Chains Forum! Register now!The RISC-V Forums, hosted by RISC-V International, are short-form, single-topic, deep-dive virtual events. This is the spirit of RISC-V events – providing technical content to…
RISC-V RV32I Instructions Format | Maven SiliconThis video explains all RV 32I Instruction formats, R, I, S, B, J, and U types, and how it simplifies the instruction decoder logic. Follow…
seL4 on RISC-V Verified to Binary CodeAuthor: Gernot Heiser, seL4 FoundationIn June 2020 we announced that the seL4 microkernel, the world’s first operating system (OS) kernel with a machine-checked proof of…
The world’s first DSP based on RISC-V ISA is about to be mass-producedRISC-V, the "youngest" ISA (Instruction Set Architecture), which was born in year 2010, has attracted many giant supporters, such as Google, Qualcomm, Western Digital, Alibaba,…
RISC-V Developer Boards to drive innovationWe are at an incredible inflection point for RISC-V. We are making history and we want you to be a part of it! RISC-V is…
Bugs: A verification engineer’s dream, a designer’s nightmareThis blog was originally published on the Axiomise website. Read the original blog. Who wants to have bug escapes? Nobody. Who wants to have bugs…
RISC-V Application to Machine Language | Maven SiliconRISC-V Application to Machine Language March 17, 2021 Sivakumar P R This video explains how a RISC-V processor executes all the software applications written in the…
Bringing the benefits of RISC-V and Renode to the Very Efficient Deep Learning in IoT projectThe EU-funded Very Efficient Deep Learning in IoT (VEDLIoT) project is underway. Launched at the end of 2020, it aims to build a next-generation IoT…
Ashling announces RiscFree™ C/C++ SDK support for Renesas’s RISC-V-based R9AG021 MCUsJune-24 2024, RISC-V European Summit, Munich, Germany. Embedded tools developer Ashling today announced support for the Renesas R9AG021 RISC-V MCUs from Renesas in Ashling’s RiscFree…
Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical ActivitiesMUNICH, Germany – June 24, 2024 – RISC-V International, the global open standards organization, announced that Andrea Gallo has joined as the organization’s new vice…
RISC-V International Names Andrea Gallo as VP, TechnologyIndustry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities MUNICH, Germany – June 24, 2024 – RISC-V International, the global open…
Ventana CEO to Deliver a Keynote at RISC-V Summit EuropeVeyron Solution — World’s Highest Performance Data RISC-V Processor and Platform — Will Be Showcased Throughout Event CUPERTINO, Calif. – June 24, 2024 – Ventana…
[VIDEO] Road to testing applications on RISC-V with QEMU and Fedora – DevConf.CZ 2024RISC-V is an open standard instruction set architecture that has potential to be widely used as an alternative to existing ARM and x86 solutions. For…
Andes Technology Showcases Leadership in AI and Automotive Applications at RISC-V Summit Europe 2024Industry-leading RISC-V solutions and live demonstrations of CPU IP are all on display at Booth #8. Discover the latest advancements from Andes’ presentations and posters!…
Breker Verification Systems Readies RISC-V CoreAssurance and SoCReady SystemVIP for Automated, Certification-level RISC-V Verification CoverageSAN JOSE, Calif., June 20, 2024 (GLOBE NEWSWIRE) -- Breker Verification Systems, whose product portfolio solves challenges across the functional and system verification process for large,…
Companies Rally RISC-V Support for AI and HPC ApplicationsAs RISC-V gains traction as an open-source alternative to Arm, several companies have announced partnerships and research to bolster the ISA. Forecasts show that AI…
[VIDEO] M1: RISC-V Overview | The Ultimate Guide to RISC-V ArchitectureWelcome to the Ultimate Guide to RISC-V Architecture. In this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V…
Follow the Leader – Synopsys Provides Broad Support for Processor EcosystemsSynopsys has expanded its ARC processor portfolio to include a family of RISC-V processors. This was originally reported on SemiWiki last October. There is also a…
Sipeed Univels the Lichee Book 4A, a Notebook for the “RISC-V Explorer”Sipeed has announced a new entry in its Lichee RISC-V family, this time putting its high-performance Lichee 4A RISC-V system-on-module into a full-size laptop chassis:…
Functional safety static analysis tool for RISC-VThe IAR safety-certified C-STAT tool is now available in the Functional Safety editions of IAR Embedded Workbench for RISC-V, ARM, and Renesas RL78 architectures. The…