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Embedded Evolution: A New RISC-V CEO & AI-Powered Platforms
SiFive and Red Hat Collaborate on Enterprise Linux for RISC-V
5 RISC-V Single-Board Computers Tested : Performance, Benchmarks, Features and Insights
AMD’s Kernel Compute Driver “AMDKFD” Can Now Be Enabled On RISC-V
Innatera’s Neuromorphic Pulsar Microcontroller Takes Center Stage at COMPUTEX 2025
5 RISC-V SBCs That Are Worth Using
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design Education
Aion Silicon wins $12M deal for RISC-V HPC, AI design work
RISC-V Turns 15 With Fast Global Adoption
Latest Semidynamics IP Redefines Heterogeneous Compute with RISC-V
15 Years of Lauterbach & RISC-V: Enabling Great Chips, Superb IP and Future-proven Applications
14 Years of RISC-V: A Journey of Innovation and Firsts
Recent developments in the Zephyr port for RISC-V
RISC-V Impact on Technology and Innovation
RISC-V for All!
Exploring the Top Highlights of the RISC-V Booth at embedded world 2024
Celebrating Women in the Global RISC-V Community
Introducing SoM1-SOC: The Most Powerful SoM Based on PolarFire® SoC FPGAIntegrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®
Meeting RISC-V Demands: S2C’s Tailored OfferingsVisit RISC-V at embedded world 2024!
RISC-V Technical Leadership UpdateJava 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse Adoptium
14 Years of RISC-V: A Journey of Innovation and FirstsRecent developments in the Zephyr port for RISC-VRISC-V Impact on Technology and InnovationRISC-V for All!Exploring the Top Highlights of the RISC-V Booth at embedded world 2024Celebrating Women in the Global RISC-V CommunityIntroducing SoM1-SOC: The Most Powerful SoM Based on PolarFire® SoC FPGAIntegrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®Meeting RISC-V Demands: S2C’s Tailored OfferingsVisit RISC-V at embedded world 2024!RISC-V Technical Leadership UpdateJava 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse Adoptium
Semidynamics Unveils Cervell™: A Scalable RISC-V Neural Processing Unit for Next-Gen AI Workloads
Semidynamics Unveils Cervell™: A Scalable RISC-V Neural Processing Unit for Next-Gen AI Workloads
Andes teams on FPGA prototyping for RISC-V development
S2C and Andes Technology Collaborating to Accelerate Advanced RISC-V SoC Development
Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based Platform
RISC-V RVA23—A Major Milestone
Testing Infineon’s virtual automotive RISC-V chip
[VIDEO] OpenHW Foundation RISC-V Cores: Empowering the Hardware Revolution for SDV
Canonical Adds the Orange Pi RV2 to Its List of Officially-Supported Ubuntu-Capable RISC-V Boards
Podcast EP282: An Overview of Andes Focus on RISC-V and the Upcoming RISC-V CON
Ubuntu developer images now available for OrangePi RV2: a low-cost RISC-V SBC
A 32-bit RISC-V processor made using molybdenum disulfide instead of silicon
Embedded Evolution: A New RISC-V CEO & AI-Powered PlatformsIn this episode of Embedded Insiders, we’re joined by RISC-V’s newest CEO, Andrea Gallo, who outlines his vision for the company’s future. From accelerating ecosystem growth…
SiFive and Red Hat Collaborate on Enterprise Linux for RISC-VIn a big announcement for the RISC-V community, SiFive and Red Hat have made public a new collaboration between the two to bring Red Hat…
5 RISC-V Single-Board Computers Tested : Performance, Benchmarks, Features and InsightsWhat if the future of computing wasn’t locked behind proprietary architectures? Imagine a world where developers and hobbyists alike could harness the power of open…
AMD’s Kernel Compute Driver “AMDKFD” Can Now Be Enabled On RISC-VFollowing all of the Linux kernel graphics driver features merged last week for the Linux 6.16 kernel, sent out this morning were the initial batch of fixes to the…
Innatera’s Neuromorphic Pulsar Microcontroller Takes Center Stage at COMPUTEX 2025In a company press release, Innatera announced its Pulsar neuromorphic microcontroller earned Best-in-Show in the Microcontrollers, Microprocessors & IP category at COMPUTEX 2025 by Embedded Computing Design.…
5 RISC-V SBCs That Are Worth UsingIf you're exploring alternatives to the Raspberry Pi, RISC-V single-board computers (SBCs) have become increasingly compelling. These open-source hardware platforms offer flexibility and performance that can rival traditional…
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design EducationProject Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and…
Aion Silicon wins $12M deal for RISC-V HPC, AI design workEnd-to-end ASIC partnership to accelerate global supercomputing market with open-standard, energy-efficient silicon. Aion Silicon announced it has secured a $12 million engagement to provide comprehensive design services for…
RISC-V Turns 15 With Fast Global AdoptionIn 2010, a modest summer project at UC Berkeley sought a suitable instruction set architecture (ISA). Now, 15 years later, RISC-V is a global alternative…
Latest Semidynamics IP Redefines Heterogeneous Compute with RISC-VVolker H. Politz, Chief Sales Officer at Semidynamics, explains why the company's Cervell™ All-in-One IP is so much more than an NPU. Remember when everyone…
15 Years of Lauterbach & RISC-V: Enabling Great Chips, Superb IP and Future-proven ApplicationsLauterbach is not only the global market leader in development tools for embedded systems; it has been part of the RISC-V community from the very…
14 Years of RISC-V: A Journey of Innovation and FirstsWhat began as a humble mission to construct a simple, efficient, and adaptable system for research endeavors and educational pursuits at the University of California…
Recent developments in the Zephyr port for RISC-VAs the open source Zephyr RTOS continues to grow in popularity, with most of the leading semiconductor vendors supporting the project as members, the open…
RISC-V Impact on Technology and InnovationBy Calista Redmond, CEO, RISC-V International RISC-V has rapidly emerged as the leading standard Instruction Set Architecture (ISA) in the world of processor design and…
RISC-V for All!What you’ll find in this blog post: Diversity is a driving force of the RISC-V RISC-V Summit Europe Travel Fund RISC-V North America Global Scholarships…
Exploring the Top Highlights of the RISC-V Booth at embedded world 2024embedded world 2024 showed great momentum for RISC-V. Throughout the event, RISC-V International members showcased cutting-edge innovations and forged invaluable connections, expanding the reach of…
Celebrating Women in the Global RISC-V CommunityCollaboration is an essential part of driving innovation forward in the growing RISC-V ecosystem. By promoting inclusivity, we strive to create a welcoming environment where…
Introducing SoM1-SOC: The Most Powerful SoM Based on PolarFire® SoC FPGABy: Mans Ahmadian, Senior Design Engineer at Sundance DSP In this blog post, we will discuss the features, benefits and applications of SoM1-SOC, a powerful…
Integrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®By: Puneet Kumar Learn more about IP Core Generation workflow from MATLAB® R2022A release onwards for PolarFire® SoC FPGA and SmartFusion® 2 family of Microchip FPGAs. Introducing IP Core Generation for…
Meeting RISC-V Demands: S2C’s Tailored OfferingsRISC-V, an open standard instruction set architecture (ISA), has captured the imaginations of engineers and innovators worldwide due to its simplicity and accessibility. This architecture…
Visit RISC-V at embedded world 2024!Step into the world of RISC-V at embedded world 2024 in Nuremberg, Germany, April 9-11! Join us as our community showcases the remarkable impact of open collaboration…
RISC-V Technical Leadership UpdateBy: Calista Redmond During the past four years RISC-V has undergone tremendous growth and transformation, both as an organization and in our leadership globally to…
Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse AdoptiumExciting news for developers and enthusiasts in the software development world! Java versions 21 and 22 are now officially supported on the RISC-V architecture, thanks…
No recent posts listed
14 Years of RISC-V: A Journey of Innovation and FirstsWhat began as a humble mission to construct a simple, efficient, and adaptable system for research endeavors and educational pursuits at the University of California…
Recent developments in the Zephyr port for RISC-VAs the open source Zephyr RTOS continues to grow in popularity, with most of the leading semiconductor vendors supporting the project as members, the open…
RISC-V Impact on Technology and InnovationBy Calista Redmond, CEO, RISC-V International RISC-V has rapidly emerged as the leading standard Instruction Set Architecture (ISA) in the world of processor design and…
RISC-V for All!What you’ll find in this blog post: Diversity is a driving force of the RISC-V RISC-V Summit Europe Travel Fund RISC-V North America Global Scholarships…
Exploring the Top Highlights of the RISC-V Booth at embedded world 2024embedded world 2024 showed great momentum for RISC-V. Throughout the event, RISC-V International members showcased cutting-edge innovations and forged invaluable connections, expanding the reach of…
Celebrating Women in the Global RISC-V CommunityCollaboration is an essential part of driving innovation forward in the growing RISC-V ecosystem. By promoting inclusivity, we strive to create a welcoming environment where…
Introducing SoM1-SOC: The Most Powerful SoM Based on PolarFire® SoC FPGABy: Mans Ahmadian, Senior Design Engineer at Sundance DSP In this blog post, we will discuss the features, benefits and applications of SoM1-SOC, a powerful…
Integrated IP Core Generation Workflow for Microchip SoC FPGAs With MathWorks®By: Puneet Kumar Learn more about IP Core Generation workflow from MATLAB® R2022A release onwards for PolarFire® SoC FPGA and SmartFusion® 2 family of Microchip FPGAs. Introducing IP Core Generation for…
Meeting RISC-V Demands: S2C’s Tailored OfferingsRISC-V, an open standard instruction set architecture (ISA), has captured the imaginations of engineers and innovators worldwide due to its simplicity and accessibility. This architecture…
Visit RISC-V at embedded world 2024!Step into the world of RISC-V at embedded world 2024 in Nuremberg, Germany, April 9-11! Join us as our community showcases the remarkable impact of open collaboration…
RISC-V Technical Leadership UpdateBy: Calista Redmond During the past four years RISC-V has undergone tremendous growth and transformation, both as an organization and in our leadership globally to…
Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse AdoptiumExciting news for developers and enthusiasts in the software development world! Java versions 21 and 22 are now officially supported on the RISC-V architecture, thanks…
Semidynamics Unveils Cervell™: A Scalable RISC-V Neural Processing Unit for Next-Gen AI WorkloadsSemidynamics has introduced Cervell™, a highly scalable and fully programmable Neural Processing Unit (NPU) architected on RISC-V. Cervell seamlessly merges CPU, vector, and tensor capabilities within…
Semidynamics Unveils Cervell™: A Scalable RISC-V Neural Processing Unit for Next-Gen AI WorkloadsSemidynamics has introduced Cervell™, a highly scalable and fully programmable Neural Processing Unit (NPU) architected on RISC-V. Cervell seamlessly merges CPU, vector, and tensor capabilities within…
Andes teams on FPGA prototyping for RISC-V developmentAndes Technology has teamed with S2C to develop an FPGA-based prototyping system for its latest RISC-V cores with extensions. The strategic deal uses S2C’s new…
S2C and Andes Technology Collaborating to Accelerate Advanced RISC-V SoC DevelopmentS2C and Andes Technology have unveiled the results of a strategic collaboration designed to significantly enhance FPGA prototyping capabilities for developers of advanced System-on-Chip (SoC)…
Andes Technology and Imagination Technologies Showcase Android 15 on High-Performance RISC-V Based PlatformSan Jose, CA – April 23, 2025 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding…
RISC-V RVA23—A Major MilestoneRISC-V Profiles, including the RVA23 Profile, help accelerate the growth of the RISC-V ecosystem by ensuring compatibility across RISC-V implementations. The 2024 RISC-V Summit North…
Testing Infineon’s virtual automotive RISC-V chipPLS Programmierbare Logik & Systeme in Germany has added support for the RISC-V open instruction set architecture to test and debug Infineon’s latest automotive processor…
[VIDEO] OpenHW Foundation RISC-V Cores: Empowering the Hardware Revolution for SDVIn this talk, Flo Wohlrab dives deep into the growing impact of industrial-grade, open-source RISC-V cores in the automotive industry, with a spotlight on the…
Canonical Adds the Orange Pi RV2 to Its List of Officially-Supported Ubuntu-Capable RISC-V BoardsCanonical has announced it is adding yet another RISC-V single-board computer to its build list for official Ubuntu Linux operating system images: the recently-released Orange…
Podcast EP282: An Overview of Andes Focus on RISC-V and the Upcoming RISC-V CONDan is joined by Marc Evans, director of business development and technology at Andes. Marc has over twenty years of experience in the use of…
Ubuntu developer images now available for OrangePi RV2: a low-cost RISC-V SBCCanonical, the publisher of Ubuntu, is excited to announce the availability of Ubuntu developer images for the new OrangePi RV2 RISC-V single board computer (SBC). We’re delighted…
A 32-bit RISC-V processor made using molybdenum disulfide instead of siliconA team of engineers at Fudan University has successfully designed, built and run a 32-bit RISC-V microprocessor that uses molybdenum disulfide instead of silicon as…