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2026 RISC-V Market Forecast

Behind The Scenes of SHD Group’s 2026 RISC-V Market Forecast

Having spent much of my career flying the flag for B2B tech, I know that belief in the thing you’re championing runs deeper than commercial success; we all want to see it make a genuine difference in the market. That's…

RISE RISC-V Developer Appreciation Program

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Semidynamics
Latest Semidynamics IP Redefines Heterogeneous Compute with RISC-V

Volker H. Politz, Chief Sales Officer at Semidynamics, explains why the company's Cervell™ All-in-One IP is so much more than an NPU. Remember when everyone…

High RISC, High Reward: RISC-V at 15
High RISC, High Reward: RISC-V at 15

As RISC-V turns 15, we explore how a summer grad project became the official compute architecture of nations – and why its story is just…

Certifying Embedded Applications Running on PolarFire® SoC FPGAs

By: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…

RISC-V International and the RISE Project Join Forces for Yocto Project Support

RISC-V International and the RISE Project are teaming up to participate in the Yocto Project. RISC-V International has upgraded from Silver to a Platinum membership…

RISC-V International Promotes Andrea Gallo to CEO

RISC-V International announces Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June…

RISC-V International Newsletter – April 2025

As we wrap up a busy Q1 for RISC-V, the excitement is building as RISC-V Summit Europe 2025 approaches, taking place from May 12-15 in…

Cost-Effective and Scalable: A Smarter Choice for RISC-V Development

The RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…

Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)

By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…

RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip Designers

Maven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced…

Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries

By Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise in…

RISC-V International at Embedded World, 11-13th March, Nuremberg Germany

embedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany between 11-13…

CHIPS Alliance and RISC-V International Invite the RISC-V Community to Participate in Updating a New Unified Memory Architecture Standard

New joint working group will enhance the OmniXtend Cache Coherency architecture SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its…

Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V International

The online courses are offered on edX.org and will make RISC-V training more accessible SAN FRANCISCO - EMBEDDED WORLD - March 2, 2021 – The…

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension Fast Track significantly accelerates the ratification of small architecture extensions Zurich – Feb.…

RISC-V International Annual Awards

RISC-V Innovation Founders Awards In recognition of the industry impact initiated by the technical leadership and generous contribution of the founding inventors and innovators of…

Stream Computing Joins RISC-V International as a Premier Member

Silicon startup Stream Computing to join the RISC-V Board of Directors and Technical Steering Committee to advance open source AI innovation Zurich – Dec. 8,…

RISCV Logo
RISC-V International Reports Another Strong Year of Growth with New Technical Milestones, Educational Programs, RISC-V Adoption and More

RISC-V sees widespread commercial adoption across industries, from embedded to AI, from IoT to HPC and beyond Zurich – Dec. 8, 2020 – RISC-V International,…

RISC-V International Announces Agenda for the Third Annual RISC-V Summit

The leading RISC-V conference will be held virtually this year, featuring keynotes, tutorials, exhibitions, networking opportunities and more WHAT: The RISC-V International Association has announced…

RISC-V Global Forum: Technology. Opportunity. Community.

The schedule for RISC-V Global Forum is live! We have an exciting lineup of keynotes, session presentations, lightning talks, ask the experts, sponsor exhibits, and…

Unlocking the Potential of Your RISC-V Laptop: The DC-ROMA Laptop II

The DC-ROMA Laptop II has undergone comprehensive upgrades in both hardware and software, offering enhanced computing power and energy efficiency, as well as extensive system…

Exploring the RISC-V Summit 2024: Technical Sessions Announced

The RISC-V Summit North America Plenary Sessions are now live on the event website. Each year, we are continually impressed with the high caliber of…

Trailblazers: Board of Directors Technical Award Winners 2024

By: Iris Zheng, Digital Marketing Intern, RISC-V International Five technical leaders were honored at RISC-V Summit Europe 2024 for their remarkable contributions to the RISC-V…

SpacemiT Key Stone K1 AI CPU has been adapted to the Fedora

SpacemiT Key Stone K1 AI CPU has been adapted to the Fedora operating system successfully. With the Fedora operating system successfully running on the MUSE…

More than 1,300 Attendees Expected at RISC-V Summit China Next Week

Check out all the impressive talks and co-located events Next week, from August 21-23, more than 1,300 attendees will gather at the Huanglong Hotel in…

Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applications

By: Barry Kavanagh, Chief Executive Officer, O.C.E. Technology Ltd. Polarfire® SoC FPGA RISC-V space applications can now take advantage of an RTOS compliant to ESA…

Open source System on Module with Microchip PolarFire SoC

The PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks…

Defining RISC-V CPUs in Renode simulation with custom instructions and extensions

By: Antmicro The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger…

Debugging of RISC-V-Based Chips Made Easy

FROM SIMPLE MICROCONTROLLERS TO COMPLEX MULTICORE SOCS RISC-V cores can be found in increasingly more chips, either as the main CPU(s) or as a companion…

New Launch: Advanced RISC-V Courses | Maven Silicon

By: Maven Silicon We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and…

How ChipFlow is Making the Impossible Possible

With Innovative technology, a collaborative spirit and a unique value proposition, Chip flow is setting itself to be the next generation of semiconductor solutions. Interview…

RT-Thread: Pioneering Real-Time Operating System for RISC-V

In the realm of modern computing architectures, the emergence of RISC-V marks a significant development, offering unprecedented openness and flexibility for processor design and implementation.…

Unlocking the Potential of Your RISC-V Laptop: The DC-ROMA Laptop II

The DC-ROMA Laptop II has undergone comprehensive upgrades in both hardware and software, offering enhanced computing power and energy efficiency, as well as extensive system…

Exploring the RISC-V Summit 2024: Technical Sessions Announced

The RISC-V Summit North America Plenary Sessions are now live on the event website. Each year, we are continually impressed with the high caliber of…

Trailblazers: Board of Directors Technical Award Winners 2024

By: Iris Zheng, Digital Marketing Intern, RISC-V International Five technical leaders were honored at RISC-V Summit Europe 2024 for their remarkable contributions to the RISC-V…

SpacemiT Key Stone K1 AI CPU has been adapted to the Fedora

SpacemiT Key Stone K1 AI CPU has been adapted to the Fedora operating system successfully. With the Fedora operating system successfully running on the MUSE…

More than 1,300 Attendees Expected at RISC-V Summit China Next Week

Check out all the impressive talks and co-located events Next week, from August 21-23, more than 1,300 attendees will gather at the Huanglong Hotel in…

Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applications

By: Barry Kavanagh, Chief Executive Officer, O.C.E. Technology Ltd. Polarfire® SoC FPGA RISC-V space applications can now take advantage of an RTOS compliant to ESA…

Open source System on Module with Microchip PolarFire SoC

The PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks…

Defining RISC-V CPUs in Renode simulation with custom instructions and extensions

By: Antmicro The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger…

Debugging of RISC-V-Based Chips Made Easy

FROM SIMPLE MICROCONTROLLERS TO COMPLEX MULTICORE SOCS RISC-V cores can be found in increasingly more chips, either as the main CPU(s) or as a companion…

New Launch: Advanced RISC-V Courses | Maven Silicon

By: Maven Silicon We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and…

How ChipFlow is Making the Impossible Possible

With Innovative technology, a collaborative spirit and a unique value proposition, Chip flow is setting itself to be the next generation of semiconductor solutions. Interview…

RT-Thread: Pioneering Real-Time Operating System for RISC-V

In the realm of modern computing architectures, the emergence of RISC-V marks a significant development, offering unprecedented openness and flexibility for processor design and implementation.…