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RISC-V RV32I J-Type | Maven Silicon Blog

RISC-V RV32I J-Type | Maven Silicon

This video explains the RV32I J-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video…

Maven SiliconFebruary 4, 2022

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation Blog

Semico Research’s New Report Predicts There Will Be 25 Billion RISC-V-Based AI SoCs By 2027 | Rich Wawrzyniak, Semico Research Corporation

Research underscores current RISC-V architecture momentum, emphasizing impressive growth in consumer, enterprise and communication markets…

RISC-V Community NewsFebruary 2, 2022

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro Blog

Open source FPGA platform for Rowhammer security testing in the data center | Antmicro

Our work together with Google and the world’s research community on detecting and mitigating the…

AntmicroJanuary 31, 2022

Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud Blog

Alibaba Cloud Opens Up IoT Technology Development Platform | Wang Cindy, Alibaba Cloud

Alibaba Cloud, the digital technology and intelligence backbone of Alibaba Group, announced it has opened…

RISC-V Community NewsJanuary 27, 2022

RISC-V RV32I S-Type | Maven Silicon BlogWhat's New

RISC-V RV32I S-Type | Maven Silicon

This video explains the RV32I S-Type instructions.  RISC-V is growing rapidly, follow this RISC-V video…

Maven SiliconJanuary 12, 2022

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS Blog

Edge AI on Low-Footprint RISC-V | Alexander Stanitzki, Fraunhofer IMS

The integration of AI algorithms on end devices (“Edge AI”, “AI of Things”, TinyML,..)  is…

RISC-V Community NewsJanuary 4, 2022

Next generation music AI engine available for RISC-V Blog

Next generation music AI engine available for RISC-V

Vancouver based software studio Cartesian Theatre Corp. and SiFive, Inc., the founder and leader in…

Kim McMahonDecember 6, 2021

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit Blog

See Western Digital’s SweRV Core family at the 2021 RISC-V Summit

RISC-V has been a very popular choice for embedded processor designs. Western Digital’s existing SweRV…

abringazeNovember 18, 2021

How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies Blog

How the Imagination RVfpga: Understanding Computer Architecture course is giving engineering under-grads real-world skills | Robert Owen, Imagination Technologies

If you were to take a look through the academic materials now available about RISC-V…

RISC-V Community NewsNovember 5, 2021

Improving the OpenLane ASIC build flow with open source SystemVerilog support | Antmicro Blog

Improving the OpenLane ASIC build flow with open source SystemVerilog support | Antmicro

Open source toolchains are key to building collaborative ecosystems, welcoming to new approaches, opportunistic/focused innovations…

AntmicroNovember 3, 2021

How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba Blog

How Alibaba is Porting RISC-V to the Android OS | Guoyin Chen, Alibaba

With the high performance Alibaba T-Head XuanTie processor coming to market, we believe it will…

RISC-V Community NewsNovember 2, 2021

Automatic SystemVerilog linting in GitHub Actions with Verible | Antmicro Blog

Automatic SystemVerilog linting in GitHub Actions with Verible | Antmicro

With the recent advances in open source ASIC development tools such as Verible, it has become easier…

AntmicroOctober 29, 2021

RISC-V RV32I I-Type | Maven Silicon Blog

RISC-V RV32I I-Type | Maven Silicon

This video explains the RV32I I-Type instructions. RISC-V is growing rapidly, follow this RISC-V video…

Maven SiliconOctober 28, 2021

Recap of the Fall 2021 CHIPS Alliance Workshop | Rob Mains, CHIPS Alliance Blog

Recap of the Fall 2021 CHIPS Alliance Workshop | Rob Mains, CHIPS Alliance

We recently held our fall 2021 CHIPS Alliance workshop with nearly 160 attendees present for…

Rob MainsOctober 26, 2021

De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISC Blog

De-RISC – The H2020 Project Which Will Create The First RISC-V Fully European Platform For Aerospace, Celebrates Its Second Anniversary | Ana Rísquez Navarro, De-RISC

The De-RISC Project celebrates its second year through the introduction of a market-ready hardware-software platform…

RISC-V Community NewsOctober 19, 2021

ZAYA Now Offers Trusted Execution Environment For RISC-V | ZAYA Blog

ZAYA Now Offers Trusted Execution Environment For RISC-V | ZAYA

Cambridge, UK - October 06, 2021, ZAYA now offers Trusted Execution Environments for RISC-V Architecture.…

RISC-V Community NewsOctober 13, 2021

RISC-V Mentorship: Formal Verification of SweRV EL2 Processor | Shashank V.M. Blog

RISC-V Mentorship: Formal Verification of SweRV EL2 Processor | Shashank V.M.

Background I was in the final year of my undergraduate degree in Electronics and Communication…

RISC-V Community NewsOctober 7, 2021

How RISC-V and CHIPS Alliance are Driving a New Unified Memory Architecture Standard | CHIPS Alliance Blog

How RISC-V and CHIPS Alliance are Driving a New Unified Memory Architecture Standard | CHIPS Alliance

RISC-V is so much more than just an ISA for processors. Because of the openness…

abringazeOctober 5, 2021

Agenda for the RISC-V Summit 2021: Together We Are Shaping the Open Era of Computing Blog

Agenda for the RISC-V Summit 2021: Together We Are Shaping the Open Era of Computing

The RISC-V Summit is the flagship event of the RISC-V community, bringing together people from…

Kim McMahonOctober 1, 2021

Privileged Specification Version 1.12 Now Open to Public Review Blog

Privileged Specification Version 1.12 Now Open to Public Review

We are delighted to announce that several specifications have been opened to public review. All…

abringazeSeptember 27, 2021

Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software Blog

Developing standards-based verification environments for extensible RISC-V processor cores | Kevin McDermott, Imperas Software

One of the appealing things about open-source is that it invites modification to the underlying…

Kevin McDermottSeptember 24, 2021

…and out come SweRVolf | Olof Kindgren, Qamcom Blog

…and out come SweRVolf | Olof Kindgren, Qamcom

One of the main FOSSi projects I've been running the last couple of years is SweRVolf,…

Olof KindgrenSeptember 22, 2021

LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT! Blog

LAST CHANCE TO SUBMIT YOUR TALK TO THE 2021 RISC-V SUMMIT!

Time is running out! The Call for Papers is open until Friday, September 10 at…

RISC-V Community NewsSeptember 9, 2021

RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions BlogWhat's New

RISC-V Cryptography Extensions Task Group Announces Public Review of the Scalar Cryptography Extensions

The Cryptography Extensions Task Group is delighted to announce the start of the public review…

abringazeSeptember 3, 2021

Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra Blog

Google Summer of Code’21 at FOSSi Foundation: TensorCore Extension for Deep Learning | Nitin Mishra

Introduction This has been a great summer! I was fortunate enough to be accepted into…

RISC-V Community NewsAugust 30, 2021