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An Introduction to Digi-Key’s RISC-V Reference Guide | Rich Miron, Digi-Key
Researchers Benchmark Experimental RISC-V Supercomputer | Anton Shilov, Tom’s Hardware
Microchip Pushes First RISC-V-based SoC FPGA to Mass Production | Jake Hertz, All About Circuits
Working with High-Level-Language Debuggers in RISC-V-Based Apps | Rafael Taubinger, Electronic Design
Lauterbach supports Fraunhofer RISC-V functional safety core | Nick Flaherty, EENews Europe
Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, Phoronix
Strong Showing for First Experimental RISC-V Supercomputer | Nicole Hemsoth, The Next Platform
First RISC-V-Based System-on-Chip (SoC) FPGA Enters Mass Production | EE Journal
Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPS$400m RISC-V design centre for Barcelona | Nick Flaherty, EE News Europe
RISC-V Researchers publish new RISC-V SoC | Robin Mitchell, ElectropagesLinux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board | Michael Larabel, Phoronix
The Accuracy and Efficiency of Posit Arithmetic | Stefan Dan Ciocirlan, Dumitrel Loghin, Lavanya Ramapantulu, Nicolae Tapus, and Yong Meng TeoHiFive Unmatched – some benchmarking results | Gábor Samu, Technical Computing Goulash
Whitepaper: Ensuring the Success of Your RISC-V Product with a Commercial-Grade Software Development Ecosystem | Engineering.com
Data Center Hot Chips, Plus Aart de Geus on AI in Chip Design | Sally Ward-Foxton , EE Times
RISC-V Pioneer SiFive Opens its First UK Office, Announces Hiring Push | Gareth Halfacree , AB Open
Study about the impact of open source software and hardware on technological independence, competitiveness and innovation in the EU economy | European Commission
Announcing the latest Open Source Peer Bonus winners | Google Open Source BlogRussian Company Develops 32-Bit RISC-V Microcontroller | Anton Shilov , Tom’s HardwareEpileptic Seizure Detection on an Ultra-Low-Power Embedded RISC-V Processor Using a Convolutional Neural Network | Andreas Bahr, Matthias Schneider, Maria Avitha Francis, Hendrik M. Lehmann, Igor Barg, Anna-Sophia Buschhoff, Peer Wulff, Thomas Strunskus, and Franz Faupel
Antmicro Doubles Down on Commitment to Zephyr RTOS as Community Grows to More Than 1,000 Contributors | The Zephyr Project
Getting Started with the ESP32-C3 RISC-V MCU | Mathias Claussen, Elektor Magazine
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The Register
An Introduction to Digi-Key’s RISC-V Reference Guide | Rich Miron, Digi-KeyRISC-V (pronounced Risk Five) is a relatively new computer technology that is being actively promoted as a competitor to ARM. A guide has been written…
Researchers Benchmark Experimental RISC-V Supercomputer | Anton Shilov, Tom’s HardwareMonte Cimone cluster combines 32 RISC-V cores. A group of researchers from the Università di Bologna and Cineca has explored an experimental eight-node 32-core RISC-V…
Microchip Pushes First RISC-V-based SoC FPGA to Mass Production | Jake Hertz, All About CircuitsMicrochip continues the push for RISC-V hardware by reaching milestones with its PolarFire system-on-a-chip (SoC) field-programmable gate array (FPGA) and Mi-V ecosystem. One major trend…
Working with High-Level-Language Debuggers in RISC-V-Based Apps | Rafael Taubinger, Electronic DesignDebugging RISC-V apps can be exhaustive and at times ineffective. However, a high-level-language debugger offers shortcuts to boost efficiency and gives you complete control over…
Lauterbach supports Fraunhofer RISC-V functional safety core | Nick Flaherty, EENews EuropeLauterbach’s debug tool now supports the EMSA5-FS functional safety processor core developed using the open RISC-V instruction set architecture. EMSA5-FS was developed by Fraunhofer Institute…
Ubuntu Working To Provide Good Support For The VisionFive Low-Cost RISC-V Board | Michael Larabel, PhoronixIn recent weeks Ubuntu developers have been working on bringing up and improving support for the Starfive VisionFive, which is one of the most promising…
Strong Showing for First Experimental RISC-V Supercomputer | Nicole Hemsoth, The Next PlatformA European team of university students has cobbled together the first RISC-V supercomputer capable of showing balanced power consumption and performance. More importantly, it demonstrates…
First RISC-V-Based System-on-Chip (SoC) FPGA Enters Mass Production | EE JournalMicrochip’s Mi-V ecosystem has enabled customers to ramp products based on PolarFire® devices more quickly, from prototypes to production. The first SoC Field Programmable Gate…
Why MIPS is Betting Big on RISC-V: Q&A with RISC-V International and MIPS | MIPSMIPS recently announced that the company is pivoting to RISC-V and introduced its first MIPS products based on RISC-V, targeting automotive, 5G and wireless networking,…
$400m RISC-V design centre for Barcelona | Nick Flaherty, EE News EuropeIntel has teamed up with the Barcelona Supercomputing Centre to establish a lab to develop the next generation of zettascale supercomputers based around the RISC-V…
RISC-V Researchers publish new RISC-V SoC | Robin Mitchell, ElectropagesAs RISC-V continues to increase in popularity, more architecture implementations are being developed, and one research team has demonstrated a 3-stage pipeline RISC-V SoC with…
Linux 5.19 Adding Support For The PolarBerry RISC-V FPGA Board | Michael Larabel, PhoronixA few days ago the RISC-V pull request landed in Linux 5.19 with support for RISC-V 32-bit (RV32) binaries on RV64, enabling the new Svpbmt extension,…
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The Accuracy and Efficiency of Posit Arithmetic | Stefan Dan Ciocirlan, Dumitrel Loghin, Lavanya Ramapantulu, Nicolae Tapus, and Yong Meng TeoMotivated by the increasing interest in the posit numeric format, in this paper we evaluate the accuracy and efficiency of posit arithmetic in contrast to…
HiFive Unmatched – some benchmarking results | Gábor Samu, Technical Computing GoulashNo sooner did I receive my SiFive HiFive Unmatched board than did the questions about the performance of the board start to come in -…
Whitepaper: Ensuring the Success of Your RISC-V Product with a Commercial-Grade Software Development Ecosystem | Engineering.comRISC-V provides a new option for microcontroller and microprocessor designs. Embedded designers now have a choice for basing their products either on one of several…
Data Center Hot Chips, Plus Aart de Geus on AI in Chip Design | Sally Ward-Foxton , EE TimesWelcome to AI with Sally, a podcast that takes a closer look at some of the most interesting technology stories on artificial intelligence and machine…
RISC-V Pioneer SiFive Opens its First UK Office, Announces Hiring Push | Gareth Halfacree , AB OpenRISC-V pioneer SiFive has opened its first office in the UK, and promises that staff there will enjoy “location flexibility” as the company looks to…
Study about the impact of open source software and hardware on technological independence, competitiveness and innovation in the EU economy | European CommissionOpen Source is increasingly used in digital technologies. This required an in-depth analysis of its current role, position and potential for the European economy. Open…
Announcing the latest Open Source Peer Bonus winners | Google Open Source BlogCongratulations to Bruno Levy for his work on the RISC-V Ecosystem on FPGAs and Carlos de Paula for his work on SymbiFlow and the RISC-V…
Russian Company Develops 32-Bit RISC-V Microcontroller | Anton Shilov , Tom’s HardwareAs we can see with the new Mikron MIK32 chip, the open-source RISC-V architecture opens doors for companies to redevelop existing microcontrollers. That's becoming even…
Epileptic Seizure Detection on an Ultra-Low-Power Embedded RISC-V Processor Using a Convolutional Neural Network | Andreas Bahr, Matthias Schneider, Maria Avitha Francis, Hendrik M. Lehmann, Igor Barg, Anna-Sophia Buschhoff, Peer Wulff, Thomas Strunskus, and Franz FaupelThe treatment of refractory epilepsy via closed-loop implantable devices that act on seizures either by drug release or electrostimulation is a highly attractive option. For…
Antmicro Doubles Down on Commitment to Zephyr RTOS as Community Grows to More Than 1,000 Contributors | The Zephyr ProjectOn the heels of its 5th anniversary and inaugural Developer Summit, the Zephyr™ Project today announces a major milestone with more than 1,000 contributors and…
Getting Started with the ESP32-C3 RISC-V MCU | Mathias Claussen, Elektor MagazineThe ESP32-C3 from Espressif has been eagerly awaited. It has just one core humming away at its heart instead of the usual two cores in…
New release of SweRVolf RISC-V SoC project aims for lower barrier to entry | Gareth Halfacree, The RegisterThe SweRVolf project, a fully open system-on-chip designed as a reference platform for Western Digital's RISC-V SweRV cores, has announced a major new release promising…