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RISC-V Microcontroller Lights Up Synth With LED Level Meter
RISC-V launches search for new CEO
HighTec compiler supports Nuclei RISC-V CPU core
SpacemiT Develops Server CPU Chip V100 for Next-Gen AI Applications
Chromium Performance Optimization on XuanTie RISC-V Processors
Multicore RISC-V Designs for Smart Automotive Apps
This Year, RISC-V Laptops Really ArriveBest of 2024: What is RISC-V and Why Has it Become Important for Java?Exploring the Power of RISC-V Processors!
Inspire Semi goes private to boost RISC-V AI chip funding
RISC-V International Newsletter – December 2024
Why we’ve levelled up on RISC-V
MachineWare at Embedded World 2023
Empowering RISC-V with open source innovation from Ubuntu
First Xuantie Partner Conference in China Highlights Growth Momentum of Thriving RISC-V Community
What to see at Embedded World 2023RISC-V Webinar with Andes and Imperas: “RISC-V Design Innovations with Custom Extensions.”Maven Silicon’s RISC-V Processor IP Verification Flow
Porting NuttX Real-Time Operating System on PolarFire® SoC FPGAAnnouncing The First International Workshop for HPC based on RISC-VXuanTie Matrix Multiply Extension InstructionsTEE SoC Based on RISC-V
CPU RTL co-simulation in Renode
Why we’ve levelled up on RISC-VMachineWare at Embedded World 2023Empowering RISC-V with open source innovation from UbuntuFirst Xuantie Partner Conference in China Highlights Growth Momentum of Thriving RISC-V CommunityWhat to see at Embedded World 2023RISC-V Webinar with Andes and Imperas: “RISC-V Design Innovations with Custom Extensions.”Maven Silicon’s RISC-V Processor IP Verification FlowPorting NuttX Real-Time Operating System on PolarFire® SoC FPGAAnnouncing The First International Workshop for HPC based on RISC-VXuanTie Matrix Multiply Extension InstructionsTEE SoC Based on RISC-VCPU RTL co-simulation in Renode
Nvidia to ship a billion of RISC-V cores in 2024Nvidia projected to ship roughly a billion RISC-V cores in its products by year’s endRISC-V reaches milestone with RVA23 profile ratificationRVA23 Profile ratification bolsters RISC-V software ecosystem
Ashling and Embecosm Announce Optimized Software Development Toolchain for Akeana at RISC-V Summit North America, 2024
SiFive HiFive Premier P550 Development Boards Now Shipping
SEGGER’s Ozone offers enhanced debugging with RISC-V SemihostingOptimizing the RISC-V BackendAre IoT Hardware Vendors Finally Going Open Source?Software-defined processors: the promise of RISC-VLDRA extends RISC-V support, adds QNXCEO interview: Chips Act boost for RISC-V
RISC-V Microcontroller Lights Up Synth With LED Level MeterThe LM3914 LED bar graph driver was an amazing chip back in the day. Along with the LM3915, its logarithmic cousin, these chips gave a…
RISC-V launches search for new CEO2024 was a year of accelerating momentum for RISC-V. Adoption grew across a diverse range of markets, the foundational new RVA23 Profile was ratified, and many new…
HighTec compiler supports Nuclei RISC-V CPU coreHighTec EDV-Systeme has added support for Nuclei System Technology’s RISC-V CPU IP to its automotive-grade LLVM open-source-based C/C++ compiler. The tools are safety-qualified according to…
SpacemiT Develops Server CPU Chip V100 for Next-Gen AI ApplicationsSpacemiT, a RISC-V AI CPU company based in China, has announced significant advancements in its development of the SpacemiT Vital Stone® V100 server CPU chip, which now offers a comprehensive…
Chromium Performance Optimization on XuanTie RISC-V ProcessorsYang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode,…
Multicore RISC-V Designs for Smart Automotive AppsWhat you’ll learn: How MIPS supports functional safety with RISC-V. What functionality is provided by MIPS RISC-V P8700 core? Why designers are looking to vendors…
This Year, RISC-V Laptops Really Arriveuried in the inner workings of your laptop is a secret blueprint, dictating the set of instructions the computer can execute and serving as the interface…
Best of 2024: What is RISC-V and Why Has it Become Important for Java?RISC stands for reduced instruction set computer, and V points to its fifth release in 2015. RISC-V is the new processor architecture to watch out for.…
Exploring the Power of RISC-V Processors!Dive into the fascinating world of RISC-V processors as we explore their architecture, benefits, and revolutionary impact on computing! In this video, we break down…
Inspire Semi goes private to boost RISC-V AI chip fundingUS RISC-V AI chip designer Inspire Semiconductor Holdings is to de-list from the TSXV Venture Exchange in Toronto today, following a move to go private.…
RISC-V International Newsletter – December 2024Message from RISC-V International As we reflect on 2024, we wanted to express our heartfelt gratitude to the entire RISC-V ecosystem. This year has been…
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Why we’ve levelled up on RISC-VAuthor: Shreyas Derashri There’s no question that disruption is coming to the CPU industry. RISC-V is here to provide an open-source alternative to proprietary CPU…
MachineWare at Embedded World 2023At Embedded World 2023 MachineWare presents SIM-V, an ultra-fast, SystemC TLM based, parallel-enabled, RISC-V instruction set simulator for early embedded software development and verification. SIM-V…
Empowering RISC-V with open source innovation from UbuntuWe are proud to join RISC-V at Embedded World again in 2023! Our team will demo Ubuntu on RISC-V boards as well as demonstrate the…
First Xuantie Partner Conference in China Highlights Growth Momentum of Thriving RISC-V CommunityThe first Xuantie Partner Conference, organized by Alibaba Group’s chip development business, T-Head, took place in Shanghai, China last week. It marks another major milestone…
What to see at Embedded World 2023RISC-V is leading the inevitable era of open computing at Embedded World 2023 in Nuremberg from March 14-16, as we bring the community together to…
RISC-V Webinar with Andes and Imperas: “RISC-V Design Innovations with Custom Extensions.”On Thursday, Feb. 23rd, Andes and Imperas held a webinar on "RISC-V Design Innovations with Custom Extensions." At the end of the formal remarks, the…
Maven Silicon’s RISC-V Processor IP Verification FlowAuthor: P R Sivakumar, Founder and CEO, Maven Silicon LinkedIn Profile: https://www.linkedin.com/in/sivapr/ 1.Introduction RISC-V is a general-purpose license-free open Instruction Set Architecture with multiple…
Porting NuttX Real-Time Operating System on PolarFire® SoC FPGANuttX Operating System NuttX is free open-source RTOS that focuses on standards compliance and small footprint. A basic version of NuttX can be run on…
Announcing The First International Workshop for HPC based on RISC-VRISC-V has seen phenomenal growth in recent years across a range of applications. One of the most exciting areas of development is High Performance Computing…
XuanTie Matrix Multiply Extension InstructionsAuthor: Qiu Jing The rise of AI has increased the demand for computing power by orders of magnitude. To meet the needs of AI for…
TEE SoC Based on RISC-VYuehai Chen, Huarun Chen, Shaozhen Chen Guangdong University of Technology In the China Postgraduate IC Innovation Competition this August, T-Head sponsored the design challenge: Building…
CPU RTL co-simulation in RenodeSupport for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of…
No recent posts listed
Why we’ve levelled up on RISC-VAuthor: Shreyas Derashri There’s no question that disruption is coming to the CPU industry. RISC-V is here to provide an open-source alternative to proprietary CPU…
MachineWare at Embedded World 2023At Embedded World 2023 MachineWare presents SIM-V, an ultra-fast, SystemC TLM based, parallel-enabled, RISC-V instruction set simulator for early embedded software development and verification. SIM-V…
Empowering RISC-V with open source innovation from UbuntuWe are proud to join RISC-V at Embedded World again in 2023! Our team will demo Ubuntu on RISC-V boards as well as demonstrate the…
First Xuantie Partner Conference in China Highlights Growth Momentum of Thriving RISC-V CommunityThe first Xuantie Partner Conference, organized by Alibaba Group’s chip development business, T-Head, took place in Shanghai, China last week. It marks another major milestone…
What to see at Embedded World 2023RISC-V is leading the inevitable era of open computing at Embedded World 2023 in Nuremberg from March 14-16, as we bring the community together to…
RISC-V Webinar with Andes and Imperas: “RISC-V Design Innovations with Custom Extensions.”On Thursday, Feb. 23rd, Andes and Imperas held a webinar on "RISC-V Design Innovations with Custom Extensions." At the end of the formal remarks, the…
Maven Silicon’s RISC-V Processor IP Verification FlowAuthor: P R Sivakumar, Founder and CEO, Maven Silicon LinkedIn Profile: https://www.linkedin.com/in/sivapr/ 1.Introduction RISC-V is a general-purpose license-free open Instruction Set Architecture with multiple…
Porting NuttX Real-Time Operating System on PolarFire® SoC FPGANuttX Operating System NuttX is free open-source RTOS that focuses on standards compliance and small footprint. A basic version of NuttX can be run on…
Announcing The First International Workshop for HPC based on RISC-VRISC-V has seen phenomenal growth in recent years across a range of applications. One of the most exciting areas of development is High Performance Computing…
XuanTie Matrix Multiply Extension InstructionsAuthor: Qiu Jing The rise of AI has increased the demand for computing power by orders of magnitude. To meet the needs of AI for…
TEE SoC Based on RISC-VYuehai Chen, Huarun Chen, Shaozhen Chen Guangdong University of Technology In the China Postgraduate IC Innovation Competition this August, T-Head sponsored the design challenge: Building…
CPU RTL co-simulation in RenodeSupport for co-simulating HDL models in Renode with Verilator has been an integral part of the framework since the 1.7.1 release, introducing a new dimension of…
Nvidia to ship a billion of RISC-V cores in 2024Although Nvidia's GPUs rely on proprietary CUDA cores that feature their instruction set architecture and support for various data formats, these cores are controlled by…
Nvidia projected to ship roughly a billion RISC-V cores in its products by year’s endIn brief: Nvidia has been quietly using the RISC-V architecture to power numerous computing devices, and deploying a substantial number of cores to paying customers. In…
RISC-V reaches milestone with RVA23 profile ratificationThe ratification of the RVA23 profile for RISC-V marks a monumental moment for the architecture, and anyone who's been following RISC-V knows that this isn't…
RVA23 Profile ratification bolsters RISC-V software ecosystemRVA23 Profile, a major release for the RISC-V software ecosystem, has been ratified, and it’s expected to help accelerate widespread implementation among toolchains and operating…
Ashling and Embecosm Announce Optimized Software Development Toolchain for Akeana at RISC-V Summit North America, 2024October 22, 2024 – Santa Clara, CA – Ashling and Embecosm are excited to announce their latest collaboration in delivering a comprehensive, optimized toolchain for…
SiFive HiFive Premier P550 Development Boards Now ShippingThe world’s highest performance RISC-V development board unlocks new opportunities for software developers to create the next era of RISC-V applications Santa Clara, Calif. –…
SEGGER’s Ozone offers enhanced debugging with RISC-V SemihostingSEGGER has expanded the capabilities of its debugger and performance analyzer, Ozone by adding semihosting support for debugging RISC-V applications. This feature now enables RISC-V developers to…
Optimizing the RISC-V BackendHello everyone! A month and a half ago, we wrote about the latest status of the RISC-V DynaRec (Dynamic Recompiler, which is the JIT backend of Box64)…
Are IoT Hardware Vendors Finally Going Open Source?The open-source revolution is expanding beyond software into hardware design. New microcontrollers from Microchip Technology and Espressif incorporate processors based on RISC-V—an open-source instruction set architecture challenging Arm’s…
Software-defined processors: the promise of RISC-VIt’s an exciting time to be involved in open source. Linux powers the world’s most critical devices, a story to which Red Hat has always…
LDRA extends RISC-V support, adds QNXLDRA has extended support for the RISC-V instruction set architecture (ISA) in its high assurance quality analysis and verification tool suite. The LDRA static analysis tools support…
CEO interview: Chips Act boost for RISC-VNick Flaherty talks to Calista Redmond, CEO of RISC-V International, on how the European Chips Act is driving the open instruction set architecture forward. “The…