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RISC-V is not an "open-source processor" | Krste Asanovic, Chairman of the Board, RISC-V

By February 18, 2020October 1st, 2020No Comments

Free and open standards are common in the computing industry, with instruction sets being an odd exception where the industry has tolerated proprietary interfaces, until now.  With the excitement around the arrival of the free and open RISC-V instruction set architecture (ISA), many are a little confused about the difference between a specification and an implementation.  There is no such thing as “the RISC-V core” — there are dozens of unique RISC-V implementations, all designed to be compatible with the burgeoning RISC-V standard software ecosystem.
The free and open RISC-V standard does enable open-source processor implementations, and there are many such open-source cores listed on the RISC-V Foundation web site.  But RISC-V is not only for open-source cores.  Commercial RISC-V ISA core vendors verify and guarantee their own core designs and provide technical support to their paying licensees, just like vendors of proprietary ISAs, except that RISC-V customers are free to choose among a large number of commercial core suppliers implementing the same standard ISA.  In fact, RISC-V already has the largest number of compatible commercial core providers compared to any other ISA in history.  This diversity of suppliers ensures a much richer variety of commercial cores with a greater stability of supply than any single proprietary ISA vendor can match.

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