V Questions with… Maven Silicon’s P R ‘Siva’ Sivakumar
Maven Silicon CEO P R Sivakumar on using RISC-V to bridge the skills gap, building a stronger engineering community and preparing new talent for an AI-driven semiconductor industry.
We Created a Single Source for All RISC-V SpecificationsThe RISC-V Ratified Specifications Library consolidates all of the available RISC-V specifications into one single, accessible repository.
Docker on RISC-V: From Release to Production in 6 DaysProject Snapshot Community-maintained Docker packages bring v29 to RISC-V64 within days of official release, not months. Fully automated pipelines compile natively on RISC-V hardware, delivering…
Using a Performance Model to Implement a Superscalar CVA6Project Snapshot How does performance modeling accelerate real hardware innovation in open RISC-V designs? In this paper, Thales demonstrates a performance model of the CVA6…
Production-Ready, Automotive-Grade, AI-Native: RISC-V at Embedded World 2026Ahead of Embedded World, we explore what our members and co-exhibitors will showcase in Nuremberg, the common threads linking their work, and what this reveals…
Support RAJA and Scientific Applications on RVV ArchitecturesProject Snapshot In this work, we aim to make RVV more accessible to scientific applications by integrating it into the RAJA performance-portability framework. RAJA is…
RISC-V Mentorship Taught Me the RISC-V ISA Is Far More Than a Reference ManualDeveloper and RISC-V Mentee Animesh Agarwal talks us through what he learned during his time on placement at Ventana Micro, and how it changed how…
Start Porting Software To RISC-V Today With Our New, Free Online CoursePorting Software to RISC-V (LFD114) is our free course for experienced engineers who need to move performance-critical software to RISC-V.
How We’re Using AI to Streamline RISC-V Regression DebuggingAI verification startup Verifaix explains how its AI Debug Agent automates regression debugging, helping RISC-V developers reduce manual verification effort and accelerate design cycles.
One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific SiliconIn this blog, Krste Asanović explains why in 2026, the state of the RISC-V union isn't just strong: it's stronger than ever.
Announcing the 2025 AI & RISC-V Gemini Credit RecipientsAnd the winners are… In September we sent out a call for proposals, looking for researchers and academics that would leverage AI to speed up…
Ocelot3: Full Vector “V” Extension for BOOMProject Snapshot Ocelot is an open-source project that enables vector support for the BOOM core. In this generation, we achieve full RVV 1.0 support. The…
How Breker Verified Frontgrade Gaisler’s NOEL-V RISC-V Core for SpaceVerification company Breker is well-versed in ensuring complex semiconductors stay robust in tough conditions, but space forced it to think differently.
Call for Proposals: AI-Driven Software Porting to RISC-VRisky Systems’ Bob Jones explains why the company’s latest core is set to revolutionize the AI SoC market, and how it intends to use it…
NASA, Google, AWS Join Stellar Line-up for RISC-V Summit North America 2025RISC-V Summit North America 2025 will bring the global RISC-V community together in Santa Clara for two days of keynotes, technical sessions, workshops, and demos.
World RISC-V Days: Hanoi Vietnam 2025Summary Under the theme “RISC-V: The Future of Open Hardware and Innovation,” the event brought together industry leaders, researchers, and tech enthusiasts for a full…
World RISC-V Days: Tokyo Japan 2025Summary Despite a bit of rainy weather, the Tokyo RISC-V community came together at a local restaurant for a lively evening of conversation, networking, and…
World RISC-V Days: Bangalore India 2025Summary A small but spirited crowd in Bangalore came together to dive into RISC-V’s future in the region—exploring RISC-V on FPGA, discussing where the local…
World RISC-V Days: Beijing 2025Summary World RISC-V Day Beijing brought the community together for a high-energy, high-impact celebration of open computing. With 200+ attendees onsite and 5,400+ participants joining…
World RISC-V Days: Hong Kong China 2025Summary World RISC-V Day Hong Kong, hosted by ExpressVPN, was a standout moment in this year’s global celebrations. As the DeepComputing team traveled across Asia to…
World RISC-V Days: Karachi Pakistan 2025Summary Dr. Farhan Ahmed Karim kicked off World RISC-V Day in Karachi with a powerful keynote, “Empowering Nations with RISC-V – A Path to Tech…
World RISC-V Days: Lahore Pakistan 2025Summary The event delivered a full, fast-paced program packed with poster sessions, networking, and hands-on challenges. Highlights included talks like “RISC-V Uncore IPs: An Introduction…
World RISC-V Days: Hsinchu City Taiwan 2025Summary Andes Technology, the NYCU Software Development Club, and the Hsinchu coding community came together in Taiwan’s semiconductor hub for a deep dive into the…
The RISC-V Newsletter is Now ‘This Week in RISC-V” on LinkedIn!Please note that the RISC-V Newsletter is now a weekly newsletter on LinkedIn. Visit This Week in RISC-V to sign up! Stay Connected with RISC-V…
Embedded Evolution: A New RISC-V CEO & AI-Powered PlatformsIn this episode of Embedded Insiders, we’re joined by RISC-V’s newest CEO, Andrea Gallo, who outlines his vision for the company’s future. From accelerating ecosystem growth…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…
RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip DesignersMaven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing LibrariesBy Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise in…
RISC-V International at Embedded World, 11-13th March, Nuremberg Germanyembedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany between 11-13…
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’sBuild safety-critical automotive, aeronautic, space, and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire FPGAs. By Evan Price, Sales…
Building on a Legacy of Security: Introducing Polar-VPXSundanceDSP, a leading provider of high-performance FPGA-based solutions, is proud to announce the latest addition to its product lineup: Polar-VPX. This cutting-edge 3U VPX form-factor…
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce RiskBy John Min John Min is VP of Customer Success at Arteris. He possesses architectural expertise that enables the successful management of design trade-offs…
How NVIDIA Shipped One Billion RISC-V Cores In 2024At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the…
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels…
RISC-V at Embedded World 2025: Innovation, Networking & Must-See SessionsThe RISC-V Pavilion returns to embedded world for 2025! Visit us in Hall 5, Stand 5-119, to discover the latest RISC-V technologies and applications and…
Accelerating RISC-V development with Tessent UltraSight-VBy: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early…
Chromium Performance Optimization on XuanTie RISC-V ProcessorsYang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode,…
CVA6 RISC-V PMP Vulnerabilities against FIAProject Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering…
Learning Computer Architecture with a Visual Simulation of RISC-V ProcessorsProject Snapshot This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle and pipelined CPUs.…
TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based CryptographyProject Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the…
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design EducationProject Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and…
Simplifying Sail Simulations and Architectural Compatibility TestingGreg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V…
TestRIG – Randomized Testing of RISC-V CPUsTestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in…
Towards an Integrated Matrix Extension: Workload Analysis of CNN Inference with QEMU TCG PlugingsIntroduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to…
Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class CoresTammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During…
How to Share Your Work and See What Others Are Building On RISC-VHello RISC-V Community, We’ve heard your feedback! Many of you expressed an interest in seeing RISC-V projects from around the world, as well as having…
Featured Work: Microarchitecture Security: The Spectre AffairAuthor: Ronan Lashermes, Hardware Security Research Engineer at Inria. Results from a joint work with Hery Andrianatrehina, Joseph Paturel, Simon Rokicki and Thomas Rubiano at…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…
RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip DesignersMaven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing LibrariesBy Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise in…
RISC-V International at Embedded World, 11-13th March, Nuremberg Germanyembedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany between 11-13…
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’sBuild safety-critical automotive, aeronautic, space, and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire FPGAs. By Evan Price, Sales…
Building on a Legacy of Security: Introducing Polar-VPXSundanceDSP, a leading provider of high-performance FPGA-based solutions, is proud to announce the latest addition to its product lineup: Polar-VPX. This cutting-edge 3U VPX form-factor…
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce RiskBy John Min John Min is VP of Customer Success at Arteris. He possesses architectural expertise that enables the successful management of design trade-offs…
How NVIDIA Shipped One Billion RISC-V Cores In 2024At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the…
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels…
RISC-V at Embedded World 2025: Innovation, Networking & Must-See SessionsThe RISC-V Pavilion returns to embedded world for 2025! Visit us in Hall 5, Stand 5-119, to discover the latest RISC-V technologies and applications and…
Accelerating RISC-V development with Tessent UltraSight-VBy: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early…
Chromium Performance Optimization on XuanTie RISC-V ProcessorsYang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode,…