One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon
In this blog, Krste Asanović explains why in 2026, the state of the RISC-V union isn't just strong: it's stronger than ever.
The Final Verification Frontier: How Breker Battle-Hardened RISC-V for SpaceVerification company Breker is well-versed in ensuring complex semiconductors stay robust in tough conditions, but space forced it to think differently.
Notes From the 2025 RISC-V Industry Development ConferenceI have just returned from the 2025 RISC-V Industry Development Conference, held across Zhuhai and Macau. Guided by the 2025 theme “Accelerating Standardization, Facilitating Connection”…
Enabling High Performance RISC-V Software for AI in the Real WorldEmbecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
We’re Showcasing RISC-V at SC25, the World’s Largest Supercomputing ConferenceI’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in…
Introducing the RISCstar Toolchain for RISC-VThe newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter StatusAt RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded DevicesAt RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…
Optimizing Hardware for Neural Network Inference using Virtual PrototypesProject Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…
New Course Coming Soon: Porting Software to RISC-V (LFD 114)The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…
Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor ProjectThe eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…
A RISC-V Based Accelerator for Post Quantum CryptographyProject Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware…
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ FlowVerification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
World RISC-V Days: Tokyo Japan 2025Summary Despite a bit of rainy weather, the Tokyo RISC-V community came together at a local restaurant for a lively evening of conversation, networking, and…
World RISC-V Days: Bangalore India 2025Summary A small but spirited crowd in Bangalore came together to dive into RISC-V’s future in the region—exploring RISC-V on FPGA, discussing where the local…
World RISC-V Days: Beijing 2025Summary World RISC-V Day Beijing brought the community together for a high-energy, high-impact celebration of open computing. With 200+ attendees onsite and 5,400+ participants joining…
World RISC-V Days: Hong Kong China 2025Summary World RISC-V Day Hong Kong, hosted by ExpressVPN, was a standout moment in this year’s global celebrations. As the DeepComputing team traveled across Asia to…
World RISC-V Days: Karachi Pakistan 2025Summary Dr. Farhan Ahmed Karim kicked off World RISC-V Day in Karachi with a powerful keynote, “Empowering Nations with RISC-V – A Path to Tech…
World RISC-V Days: Lahore Pakistan 2025Summary The event delivered a full, fast-paced program packed with poster sessions, networking, and hands-on challenges. Highlights included talks like “RISC-V Uncore IPs: An Introduction…
World RISC-V Days: Hsinchu City Taiwan 2025Summary Andes Technology, the NYCU Software Development Club, and the Hsinchu coding community came together in Taiwan’s semiconductor hub for a deep dive into the…
RISC-V International Newsletter – July 2025A Note From Our CEO Welcome to the latest RISC-V newsletter, my first as the new CEO at RISC-V International. I’m incredibly excited to step…
Embedded Evolution: A New RISC-V CEO & AI-Powered PlatformsIn this episode of Embedded Insiders, we’re joined by RISC-V’s newest CEO, Andrea Gallo, who outlines his vision for the company’s future. From accelerating ecosystem growth…
High RISC, High Reward: RISC-V at 15As RISC-V turns 15, we explore how a summer grad project became the official compute architecture of nations – and why its story is just…
RISC-V International and the RISE Project Join Forces for Yocto Project SupportRISC-V International and the RISE Project are teaming up to participate in the Yocto Project. RISC-V International has upgraded from Silver to a Platinum membership…
RISC-V International Promotes Andrea Gallo to CEORISC-V International announces Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…
RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip DesignersMaven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing LibrariesBy Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise in…
RISC-V International at Embedded World, 11-13th March, Nuremberg Germanyembedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany between 11-13…
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’sBuild safety-critical automotive, aeronautic, space, and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire FPGAs. By Evan Price, Sales…
Building on a Legacy of Security: Introducing Polar-VPXSundanceDSP, a leading provider of high-performance FPGA-based solutions, is proud to announce the latest addition to its product lineup: Polar-VPX. This cutting-edge 3U VPX form-factor…
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce RiskBy John Min John Min is VP of Customer Success at Arteris. He possesses architectural expertise that enables the successful management of design trade-offs…
How NVIDIA Shipped One Billion RISC-V Cores In 2024At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the…
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels…
RISC-V at Embedded World 2025: Innovation, Networking & Must-See SessionsThe RISC-V Pavilion returns to embedded world for 2025! Visit us in Hall 5, Stand 5-119, to discover the latest RISC-V technologies and applications and…
Accelerating RISC-V development with Tessent UltraSight-VBy: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early…
Chromium Performance Optimization on XuanTie RISC-V ProcessorsYang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode,…
Simplifying Sail Simulations and Architectural Compatibility TestingGreg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V…
TestRIG – Randomized Testing of RISC-V CPUsTestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in…
Towards an Integrated Matrix Extension: Workload Analysis of CNN Inference with QEMU TCG PlugingsIntroduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to…
Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class CoresTammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During…
How to Share Your Work and See What Others Are Building On RISC-VHello RISC-V Community, We’ve heard your feedback! Many of you expressed an interest in seeing RISC-V projects from around the world, as well as having…
Featured Work: Microarchitecture Security: The Spectre AffairAuthor: Ronan Lashermes, Hardware Security Research Engineer at Inria. Results from a joint work with Hery Andrianatrehina, Joseph Paturel, Simon Rokicki and Thomas Rubiano at…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…
RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip DesignersMaven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing LibrariesBy Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise in…
RISC-V International at Embedded World, 11-13th March, Nuremberg Germanyembedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany between 11-13…
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’sBuild safety-critical automotive, aeronautic, space, and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire FPGAs. By Evan Price, Sales…
Building on a Legacy of Security: Introducing Polar-VPXSundanceDSP, a leading provider of high-performance FPGA-based solutions, is proud to announce the latest addition to its product lineup: Polar-VPX. This cutting-edge 3U VPX form-factor…
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce RiskBy John Min John Min is VP of Customer Success at Arteris. He possesses architectural expertise that enables the successful management of design trade-offs…
How NVIDIA Shipped One Billion RISC-V Cores In 2024At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the…
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels…
RISC-V at Embedded World 2025: Innovation, Networking & Must-See SessionsThe RISC-V Pavilion returns to embedded world for 2025! Visit us in Hall 5, Stand 5-119, to discover the latest RISC-V technologies and applications and…
Accelerating RISC-V development with Tessent UltraSight-VBy: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early…
Chromium Performance Optimization on XuanTie RISC-V ProcessorsYang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode,…