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OpenChip

V Questions with… Openchip’s Cesc Guim and Marc Fernández

'V Questions with…' uncovers the backstory to a RISC-V member's latest work in 5 questions. Here, I talk to the duo behind BER10, the sovereign SoC that Barcelona's Openchip taped out in under two years.

2025 RISC-V Industry Development Conference
Notes From the 2025 RISC-V Industry Development Conference

I have just returned from the 2025 RISC-V Industry Development Conference, held across Zhuhai and Macau. Guided by the 2025 theme “Accelerating Standardization, Facilitating Connection”…

Enabling High Performance RISC-V Software for AI in the Real World

Embecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…

RISC-V and SC25 logos
We’re Showcasing RISC-V at SC25, the World’s Largest Supercomputing Conference

I’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in…

riscstar
Introducing the RISCstar Toolchain for RISC-V

The newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…

Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of ISO/IEC JTC 1, on stage at RISC-V Summit North America 2025
RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter Status

At RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…

Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded Devices

At RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…

Optimizing Hardware for Neural Network Inference using Virtual Prototypes

Project Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…

New Course Coming Soon: Porting Software to RISC-V (LFD 114)

The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…

Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor Project

The eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…

A RISC-V Based Accelerator for Post Quantum Cryptography

Project Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware…

A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ Flow

Verification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…

New to RISC-V? Here’s Why Summit 2025 is the Place to Begin Your Journey

The 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…

High RISC, High Reward: RISC-V at 15
High RISC, High Reward: RISC-V at 15

As RISC-V turns 15, we explore how a summer grad project became the official compute architecture of nations – and why its story is just…

RISC-V International and the RISE Project Join Forces for Yocto Project Support

RISC-V International and the RISE Project are teaming up to participate in the Yocto Project. RISC-V International has upgraded from Silver to a Platinum membership…

RISC-V International Promotes Andrea Gallo to CEO

RISC-V International announces Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June…

RISC-V International Newsletter – April 2025

As we wrap up a busy Q1 for RISC-V, the excitement is building as RISC-V Summit Europe 2025 approaches, taking place from May 12-15 in…

RISC-V launches search for new CEO

2024 was a year of accelerating momentum for RISC-V.  Adoption grew across a diverse range of markets, the foundational new RVA23 Profile was ratified, and many new…

RISC-V International Newsletter – December 2024

Message from RISC-V International As we reflect on 2024, we wanted to express our heartfelt gratitude to the entire RISC-V ecosystem. This year has been…

RISC-V CEO Calista Redmond resigns after 5+ years of progress

By: Calista Redmond | CEO, RISC-V International  It is with deep gratitude that I announce my resignation from RISC-V International as I’ve accepted a new…

RISC-V Announces Ratification of the RVA23 Profile Standard

Vector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads including AI/ML & cryptography, and enterprise hardware, operating systems and…

RISC-V International Newsletter – September 2024

Message from RISC-V International The countdown is on! RISC-V Summit North America takes place on October 22-23 at the Santa Clara Convention Center. The Summit is…

RISC-V International Names Andrea Gallo as VP, Technology

Industry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities MUNICH, Germany – June 24, 2024 – RISC-V International, the global…

RISC-V International Newsletter – June 2024

Message from RISC-V International Events are key to the success of RISC-V, where we come together to share the latest developments and build the relationships…

On May 18th RISC-V is turning 14! To celebrate we are giving away 14 bundles of the RISC-V Fundamentals Course and RISC-V Foundational Associate Certification…

Exploring RISC-V ISA Developments and Technical Highlights from 2024

2024 has been a year of great technical progress for the RISC-V ISA. Our 75 Committees and Groups, staffed by contributors from RISC-V member organizations…

RISC-V 2024: A Year of Global Growth and Innovation

As 2024 comes to a close, it’s clear that this has been a transformative year for RISC-V. From achieving industry firsts to driving innovation across…

S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC

S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC December 19, 2024 – S2C, a global leader in FPGA-based prototyping solutions,…

My Journey with the RISC-V Mentorship | Sailing Downstream II

by Linda Njau, RISC-V Mentee at Ventana Micro SystemsI came across the Linux/RISC-V mentorship while searching for an internship, and my curiosity was sparked by…

XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative Computing

Weitong Su, Alibaba DAMO Academy Co-processors are specialized units designed to assist the main processor in executing specific tasks, such as graphics processing and signal…

Enhancing the Future of AI/ML with Attached Matrix Extension

Zhao Jiang, Alibaba DAMO Academy In recent years, the rapid advancement of AI technologies, particularly deep learning, has significantly increased the demand for computing power,…

Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career Pivot

Andrea Gallo, RVFA Vice President of Technology at RISC-V InternationalAfter decades of a highly successful, Arm-focused career, Andrea Gallo was ready to take his professional…

Triton kernel performance on RISC-V CPU

Introduction to Triton Triton is an open-source, Python-based Domain-Specific Language (DSL) developed by OpenAI to simplify the writing of high-performance GPGPU code. It was first…

Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMs

By Deke Wang and David Chen, Stream Computing In the wave of digital transformation, the intelligent upgrade of community services has become key to improving…

Stream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix Implementation

By Fujie Fan and David Chen, Stream Computing Background: In order to solve the problem of instruction fragmentation of RISC-V in AI field and accelerate…

Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoT

DOME Cybersecurity provides a flexible Software Development Kit (SDK) for connecting the PolarFire FPGA to the IoT  By: Harry Ostaffe Vice President, Marketing @ Veridify…

RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source Innovations

On October 17, the inaugural RISC-V Eco-system Development Forum, held as part of the  Guangdong-Hong Kong-Macao Greater Bay Area Semiconductor Industry Expo, took place  at…

Exploring RISC-V ISA Developments and Technical Highlights from 2024

2024 has been a year of great technical progress for the RISC-V ISA. Our 75 Committees and Groups, staffed by contributors from RISC-V member organizations…

RISC-V 2024: A Year of Global Growth and Innovation

As 2024 comes to a close, it’s clear that this has been a transformative year for RISC-V. From achieving industry firsts to driving innovation across…

S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC

S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC December 19, 2024 – S2C, a global leader in FPGA-based prototyping solutions,…

My Journey with the RISC-V Mentorship | Sailing Downstream II

by Linda Njau, RISC-V Mentee at Ventana Micro SystemsI came across the Linux/RISC-V mentorship while searching for an internship, and my curiosity was sparked by…

XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative Computing

Weitong Su, Alibaba DAMO Academy Co-processors are specialized units designed to assist the main processor in executing specific tasks, such as graphics processing and signal…

Enhancing the Future of AI/ML with Attached Matrix Extension

Zhao Jiang, Alibaba DAMO Academy In recent years, the rapid advancement of AI technologies, particularly deep learning, has significantly increased the demand for computing power,…

Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career Pivot

Andrea Gallo, RVFA Vice President of Technology at RISC-V InternationalAfter decades of a highly successful, Arm-focused career, Andrea Gallo was ready to take his professional…

Triton kernel performance on RISC-V CPU

Introduction to Triton Triton is an open-source, Python-based Domain-Specific Language (DSL) developed by OpenAI to simplify the writing of high-performance GPGPU code. It was first…

Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMs

By Deke Wang and David Chen, Stream Computing In the wave of digital transformation, the intelligent upgrade of community services has become key to improving…

Stream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix Implementation

By Fujie Fan and David Chen, Stream Computing Background: In order to solve the problem of instruction fragmentation of RISC-V in AI field and accelerate…

Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoT

DOME Cybersecurity provides a flexible Software Development Kit (SDK) for connecting the PolarFire FPGA to the IoT  By: Harry Ostaffe Vice President, Marketing @ Veridify…

RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source Innovations

On October 17, the inaugural RISC-V Eco-system Development Forum, held as part of the  Guangdong-Hong Kong-Macao Greater Bay Area Semiconductor Industry Expo, took place  at…