Production-Ready, Automotive-Grade, AI-Native: RISC-V at Embedded World 2026
Ahead of Embedded World, we explore what our members and co-exhibitors will showcase in Nuremberg, the common threads linking their work, and what this reveals about the embedded landscape in 2026.
Arteris’ Multi-Die Solution for the RISC-V Ecosystemby Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
CVA6 RISC-V PMP Vulnerabilities against FIAProject Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering…
World RISC-V Days: Hanoi Vietnam 2025Summary Under the theme “RISC-V: The Future of Open Hardware and Innovation,” the event brought together industry leaders, researchers, and tech enthusiasts for a full…
World RISC-V Days: Tokyo Japan 2025Summary Despite a bit of rainy weather, the Tokyo RISC-V community came together at a local restaurant for a lively evening of conversation, networking, and…
World RISC-V Days: Bangalore India 2025Summary A small but spirited crowd in Bangalore came together to dive into RISC-V’s future in the region—exploring RISC-V on FPGA, discussing where the local…
World RISC-V Days: Beijing 2025Summary World RISC-V Day Beijing brought the community together for a high-energy, high-impact celebration of open computing. With 200+ attendees onsite and 5,400+ participants joining…
World RISC-V Days: Hong Kong China 2025Summary World RISC-V Day Hong Kong, hosted by ExpressVPN, was a standout moment in this year’s global celebrations. As the DeepComputing team traveled across Asia to…
World RISC-V Days: Karachi Pakistan 2025Summary Dr. Farhan Ahmed Karim kicked off World RISC-V Day in Karachi with a powerful keynote, “Empowering Nations with RISC-V – A Path to Tech…
World RISC-V Days: Lahore Pakistan 2025Summary The event delivered a full, fast-paced program packed with poster sessions, networking, and hands-on challenges. Highlights included talks like “RISC-V Uncore IPs: An Introduction…
World RISC-V Days: Hsinchu City Taiwan 2025Summary Andes Technology, the NYCU Software Development Club, and the Hsinchu coding community came together in Taiwan’s semiconductor hub for a deep dive into the…
NVIDIA on RVA23: “We Wouldn’t Have Considered Porting CUDA to RISC-V Without It”By setting a clear, stable standard, the RVA23 profile’s ratification is spurring top vendors to align on a common RISC-V hardware goal. All we need…
7 Critical Components of the Car of TomorrowWith IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every…
RISC-V International Achieves Milestone with Ratification of 40 Specifications in Two YearsLatest Ratifications Primarily Target Core Areas of Efficiency, Vector, and Virtualization ZURICH – April 4, 2024 – RISC-V International, the global standards organization, today announced…
RISC-V International to Showcase the Latest RISC-V Developments at embedded world 2024WHO: RISC-V International WHAT: RISC-V International will be exhibiting at embedded world 2024, sharing the latest developments from its community and showcasing a range of…
RISC-V International Newsletter – March 2024Message from RISC-V International 2024 is now well underway and we have some exciting new developments from our members worldwide! RISC-V is truly a global…
RISC-V International Newsletter – December 2023Message from RISC-V International As we look back on 2023, we wanted to express our gratitude to the entire RISC-V ecosystem. Throughout the year, we…
RISC-V International Marks Banner Year for RISC-V Adoption, Technical Momentum, and Community EngagementRISC-V adoption continues to expand across key vertical markets including aerospace, AI/ML, automotive, data center, embedded, HPC, and security Santa Clara, Calif. – Nov. 7,…
RISC-V International Newsletter – November 2023Message from RISC-V International Greetings! We’re in the final countdown to RISC-V Summit North America, which runs Nov. 6-8 in Santa Clara, CA. The anticipation and…
RISC-V International Newsletter – September 2023Message from RISC-V International RISC-V is inevitable! During the past few months, the RISC-V ecosystem has continued to grow globally. We are witnessing incredible adoption,…
RISC-V International Newsletter – May/June 2023Message from RISC-V International The growth and reach of the RISC-V ecosystem continues to inspire me during 2023! We are seeing incredible adoption across a…
Ashling and Imagination announce Ashling’s RiscFree™ C/C++ SDK support for RISC-V-based Catapult family.Embedded World, Mar-14 2023, Nuremberg, Germany. Ashling and Imagination Technologies announced today that Ashling’s RiscFree SDK will provide software development support for Imagination’s Catapult RISC-V-based…
RISC-V Newsletter – March 2, 2023RISC-V Momentum We’re off to an incredible start in 2023! We have already ratified several extensions and are on course to complete six ratifications in…
First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across IndustriesThe Barcelona RISC-V Summit from June 5-9 to focus on industries such as Automotive, High Performance Compute/Data Center, and Security; Call for Submissions and Sponsorships…
RISC-V Honors Outstanding Technical and Community Contributions for 2022Recipients Selected from Tens of Thousands of Engineers Working on RISC-V Initiatives Globally San Jose, Calif. – Dec. 21, 2022 – RISC-V International, the global…
RISC-V Summit North America 2024: Keynotes and Industry TracksThe RISC-V Summit North America 2024 is a pivotal event for the RISC-V community, bringing together innovators, developers, and thought leaders who are driving advancements…
Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!The RISC-V Summit North America 2024 is fast approaching, and it's a must-attend event for those interested in shaping the future RISC-V and open standards.…
Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEEBy Erhu Feng (Shanghai Jiao Tong University), Qingyu Shang (Shanghai Jiao Tong University), Yu-Chien Lin (Andes), Che-Chia Chang (Andes), Bing Gui (Nuclei) Introduction There has…
AI/ML Innovations at RISC-V Summit North America: A Track to WatchRegistration prices for RISC-V Summit North America 2024 increase after Oct 11. Register today to sit in on AI/ML presentations and more. Artificial Intelligence (AI)…
Join Us for the RISC-V Hackathon at Summit North America 2024!We’re excited to team up with our members Andes, Codasip, and Tactical Computing Laboratories to bring you an in-person hackathon at this year’s RISC-V Summit…
RISC-V Processor Design – Free YouTube Course by Maven SiliconIn this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how chip designers design various chips,…
Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze ToolsBy: Matej Antonijevic (TASKING) Developers who have struggled with achieving real-time performance and security in embedded systems can now look forward to unprecedented capabilities thanks…
Debugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® ToolsBy: Frank Riemenschneider, Senior Marketing Engineer at Lauterbach GmbH Microchip's PolarFire® System-on-Chip Field-Programmable Gate Array (SoC FPGA) family implements a total of five SiFive U54…
Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged UpstreamThe Box64 RISC-V backend has implemented scalar instructions to emulate x86_64 vector extensions like MMX and SSE*, ensuring good compatibility with the rv64gc architecture. However,…
TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector ProcessorBy Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications…
Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoCNX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024—…
Leveraging a Passion for Logic into a RISC-V CareerThe path to success for an IT career is often paved with curiosity, dedication and a willingness to evolve. Victor Labián Carro, RVFA, now a…
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RISC-V Summit North America 2024: Keynotes and Industry TracksThe RISC-V Summit North America 2024 is a pivotal event for the RISC-V community, bringing together innovators, developers, and thought leaders who are driving advancements…
Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!The RISC-V Summit North America 2024 is fast approaching, and it's a must-attend event for those interested in shaping the future RISC-V and open standards.…
Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEEBy Erhu Feng (Shanghai Jiao Tong University), Qingyu Shang (Shanghai Jiao Tong University), Yu-Chien Lin (Andes), Che-Chia Chang (Andes), Bing Gui (Nuclei) Introduction There has…
AI/ML Innovations at RISC-V Summit North America: A Track to WatchRegistration prices for RISC-V Summit North America 2024 increase after Oct 11. Register today to sit in on AI/ML presentations and more. Artificial Intelligence (AI)…
Join Us for the RISC-V Hackathon at Summit North America 2024!We’re excited to team up with our members Andes, Codasip, and Tactical Computing Laboratories to bring you an in-person hackathon at this year’s RISC-V Summit…
RISC-V Processor Design – Free YouTube Course by Maven SiliconIn this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how chip designers design various chips,…
Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze ToolsBy: Matej Antonijevic (TASKING) Developers who have struggled with achieving real-time performance and security in embedded systems can now look forward to unprecedented capabilities thanks…
Debugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® ToolsBy: Frank Riemenschneider, Senior Marketing Engineer at Lauterbach GmbH Microchip's PolarFire® System-on-Chip Field-Programmable Gate Array (SoC FPGA) family implements a total of five SiFive U54…
Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged UpstreamThe Box64 RISC-V backend has implemented scalar instructions to emulate x86_64 vector extensions like MMX and SSE*, ensuring good compatibility with the rv64gc architecture. However,…
TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector ProcessorBy Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications…
Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoCNX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024—…
Leveraging a Passion for Logic into a RISC-V CareerThe path to success for an IT career is often paved with curiosity, dedication and a willingness to evolve. Victor Labián Carro, RVFA, now a…