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Video: Pipelining of RISC-V processor

This is a short discussion of the concept of "pipelining" of RISC-V processor. It was created to supplement the lectures of a course focused on…

Video: Stall vs. Flush in RISC-V processor

This is a short discussion of the concept of "pipelining" of RISC-V processor. It was created to supplement the lectures of a course focused on…

Xen releases a new version 4.15 after a slightly delayed development process | Simon Sharwood, APAC Editor, The Register

The Xen project has released another upgrade to its open source hypervisor. Development of this new cut – version 4.15 – proved a little trickier…

RISC-V Application to Machine Language | Maven Silicon

RISC-V Application to Machine Language March 17, 2021 Sivakumar P R This video explains how a RISC-V processor executes all the software applications written in the…

Open Source Leader Shares the Importance of Knowing and Embracing Your Strengths with Executive Kim McMahon | The Digital Executive

RISC-V International's Director of Visibility & Community Engagement, Kim McMahon, joins Coruzant Technologies for the Digital Executive podcast. She shares that you have to really…

RISC-V Star Rises Among Chip Developers Worldwide | Jeremy Hsu, IEEE Spectrum

The upstart RISC-V chip architecture has found international traction with its customizable open-source design and lack of licensing fees Read the full article.

Efinix® Announces Expansion of High-Performance Titanium FPGA Product Line | Press Release

Titanium Product Line Expands to 1M Logic Elements SANTA CLARA, Calif.--(BUSINESS WIRE)--Efinix®, an innovator in programmable product platforms and technology, today announced the expansion of…

Get Ready for the Most Interesting CPU Market We’ve Seen in Decades | Joel Hruska , Extreme Tech

For most of the last 2.5 decades, the PC CPU industry has been dominated by a single architecture: x86. While the 1990s opened with a…

Week In Review: Design, Low Power | Jessee Allen, Semiconductor Engineering

Standards CHIPS Alliance and RISC-V International will work jointly to update the OmniXtend Cache Coherency specification. The two groups formed a new OmniXtend working group…

DARPA adds RISC-V to its Toolbox: Defense researchers can get special access to SiFive chip designs | Katyanna Quach

Engineers and scientists working on American military research programs can now access RISC-V processor core designs and associated blueprints through DARPA's Toolbox, and use the…

An Ultra-Low Power RISC-V Chip and a Clever Neural Network Give This Crazyflie “Top-Notch” Autonomy | Gareth Halfacree

GAP8 "Parallel Ultra-Low Power" chip draws just 86mW to drive a 135 frames-per-second autonomous flight system with pose estimation. Read the full article.

RISC-V Extension Boasts Dramatic Improvements in Ultra-Low Power IoT Wireless Signal Processing | Gareth Halfacree

Extensions to the open source ISA offer "substantial energy savings" for common IoT protocols including LoRa and Bluetooth Low Energy. Read the full article.

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RISC-V Deep Dive, CTO Interview | Dan Olds, Radio Free HPC

More on the podcast and to listen.]]>