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Highlights from the RISC-V Summit 2024
Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoT
How to Share Your Work and See What Others Are Building On RISC-V
Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI Inference
Interview with RISC-V International: High-Performance Chips, AI, Ecosystem Fragmentation, and The Future
RISC-V Oozes Confidence with RVA23 Profile Ratification
4 Highlights From the RISC-V Summit North America
DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu Desktop
RISC-V User-Space Pointer Masking Appears Ready For Linux 6.13
Denso seals Quadric deal for RISC-V AI coreRISC-V CPU demoed with RX 7900 XTX GPU in Debian Linux — AMD flagship GPU paired with Milk-V Megrez board and SiFive P550 cores
RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source Innovations
Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | Microchip
Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | Antmicro
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies Inc
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalEverything RISC-V at the Design Automation Conference! | RISC-V International
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudPolarFire® SoC FPGA in Conclusive RCHD-PF System Module | Microchip
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep Computing
SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, Syntacore
Democratizing Chiplet-Based Processor Design | Ventana Micro Systems
RISC-V Vector Processing is Taking Off | SiFive
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies
Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | MicrochipCo-developing Machine Learning with a RISC-V vector core using Renode for Google Research | AntmicroAccelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies IncRISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalEverything RISC-V at the Design Automation Conference! | RISC-V InternationalProgress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudPolarFire® SoC FPGA in Conclusive RCHD-PF System Module | MicrochipDeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep ComputingSoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, SyntacoreDemocratizing Chiplet-Based Processor Design | Ventana Micro SystemsRISC-V Vector Processing is Taking Off | SiFiveGreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves Technologies
New RISC-V Innovations Lead AI to Open Standard[VIDEO] Join us for This Year’s RISC-V Summit
SEALSQ introduces new RISC-V secure hardware platform for IoT security
DeepComputing Announces the Launch of the DC-ROMA RISC-V Pad II!Microchip unveils PIC64 family of RISC-V multicore processor chips for Earth and for space[VIDEO] Checking Out The Teensy Tiny RISC-V NanoKVM!Harnessing power of RISC-V, Generative AI: Expert hardware security architect Avani Dave’s visionRISC-V cluster IP for data centre SoCs and chipletsSiFive moves into RISC-V datacentre AI processor IP
Akeana exits stealth mode with comprehensive RISC-V processor portfolio
SiFive Announces New High-performance RISC-V Datacenter Processor for Demanding AI Workloads
Highlights from the RISC-V Summit 2024What you’ll learn: The state of RISC-V, including new RISC-V announcements. A look at some good video presentations at the 2024 RISC-V Summit. RISC-V trends…
Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoTDOME Cybersecurity provides a flexible Software Development Kit (SDK) for connecting the PolarFire FPGA to the IoT By: Harry Ostaffe Vice President, Marketing @ Veridify…
How to Share Your Work and See What Others Are Building On RISC-VHello RISC-V Community, We’ve heard your feedback! Many of you expressed an interest in seeing RISC-V projects from around the world, as well as having…
Fractile Licenses Andes Technology’s RISC-V Vector Processor as It Builds Radical New Chip to Accelerate AI InferenceSan Jose, CA — Oct. 22, 2024 — Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and Founding Premier member of RISC-V…
Interview with RISC-V International: High-Performance Chips, AI, Ecosystem Fragmentation, and The FutureRISC-V is an industry standard instruction set architecture (ISA) born in UC Berkeley. RISC-V is the fifth iteration in the lineage of historic RISC processors.…
RISC-V Oozes Confidence with RVA23 Profile RatificationLast week’s RISC-V Summit in Santa Clara, Calif., had an air of confidence that we have not seen at previous summits. There was much for…
4 Highlights From the RISC-V Summit North AmericaIn this roundup, we discuss several announcements from last week's summit pushing RISC-V adoption and processing power. Four companies, including Andes Technology, RISC-V International, Arteris,…
DeepComputing and Andes Technology Partner to Develop the World’s First RISC-V AI PC with 7nm QiLai SoC, Featuring Ubuntu DesktopSan Jose, CA — Oct 22, 2024 — DeepComputing, a pioneer in RISC-V innovation, today announced a strategic partnership with Andes Technology Corporation, a leading provider of high-efficiency, low-power…
RISC-V User-Space Pointer Masking Appears Ready For Linux 6.13It looks like the upcoming Linux 6.13 cycle will be adding RISC-V support for user-space pointer masking and tagged address ABI. RISC-V pointer masking can be used…
Denso seals Quadric deal for RISC-V AI coreLeading Japanese automotive supplier Denso is expanding its semiconductor business through a development license agreement for a Neural Processing Unit (NPU) AI core from Quadric…
RISC-V CPU demoed with RX 7900 XTX GPU in Debian Linux — AMD flagship GPU paired with Milk-V Megrez board and SiFive P550 coresRISC-V firm Milk-V demonstrated that it can get AMD’s RX 7900 XTX graphics card to work on one of its RISC-V boards. The PC shown in the…
RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source InnovationsOn October 17, the inaugural RISC-V Eco-system Development Forum, held as part of the Guangdong-Hong Kong-Macao Greater Bay Area Semiconductor Industry Expo, took place at…
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Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | MicrochipCustomers often require support to bring up new boards and architectures on Linux. Our Mi-V ecosystem partner, Codethink’s specialty is board bring-up and they perform…
Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | AntmicroThe landscape of Machine Learning software libraries and models is evolving rapidly, and to satisfy the ever-increasing demand for memory and compute while managing latency,…
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies IncMachine learning (ML) recommendation workloads have demanding performance and memory requirements and, to date, have largely been run on servers with x86 processors. To accelerate…
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalIn Spring 2022, various mentorship projects were offered by RISC-V International on the LFX platform of the Linux Foundation. I got selected for one of…
Everything RISC-V at the Design Automation Conference! | RISC-V InternationalThe Design Automation Conference is here and we're thrilled to share look at all the RISC-V happenings during the show. If you are interested in…
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudLast year Alibaba T-Head reported that the basic features of Android had been ported onto RISC-V-based Xuantie cores. Since then more effort has been spent…
PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | MicrochipOperational Technology (OT) and Transportation and Industrial Control Systems (ICS) are often forced to make concessions regarding security and updates to deliver critical functionality without…
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep ComputingROMA development platform features forthcoming quad-core RISC-V processor for fastest, seamless RISC-V software development experience. DeepComputing and Xcalibyte today opened pre-orders for the industry’s first…
SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, SyntacoreYADRO and Syntacore hosted the first ever engineering hackathon for students in Russia. The event was organized in association with National Research University of Electronic…
Democratizing Chiplet-Based Processor Design | Ventana Micro SystemsBy Bob Wheeler, Principal Analyst, The Linley Group Chiplet-based designs promise reduced development costs and faster time to market, but they’ve been exclusive to large…
RISC-V Vector Processing is Taking Off | SiFiveThe RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector…
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves TechnologiesLocated in the micro-and nano-electronics hotspot of Grenoble, GreenWaves is a fabless semiconductor startup that designs and brings to market advanced ultra-low-power AI and DSP…
No recent posts listed
Porting GNOME OS to Microchip’s PolarFire® SoC FPGA Icicle Kit for the First Time | MicrochipCustomers often require support to bring up new boards and architectures on Linux. Our Mi-V ecosystem partner, Codethink’s specialty is board bring-up and they perform…
Co-developing Machine Learning with a RISC-V vector core using Renode for Google Research | AntmicroThe landscape of Machine Learning software libraries and models is evolving rapidly, and to satisfy the ever-increasing demand for memory and compute while managing latency,…
Accelerating ML Recommendation With Over 1,000 RISC-V/Tensor Processors on Esperanto’s ET-SoC-1 Chip | David R. Ditzel, Esperanto Technologies IncMachine learning (ML) recommendation workloads have demanding performance and memory requirements and, to date, have largely been run on servers with x86 processors. To accelerate…
RISC-V Compressed Instructions for SERV | Abdul Wadood, LFX Mentorship at RISC-V InternationalIn Spring 2022, various mentorship projects were offered by RISC-V International on the LFX platform of the Linux Foundation. I got selected for one of…
Everything RISC-V at the Design Automation Conference! | RISC-V InternationalThe Design Automation Conference is here and we're thrilled to share look at all the RISC-V happenings during the show. If you are interested in…
Progress in Porting Android onto RISC-V: Android 12 upgrade, vendor modules and TensorFlow Lite | Mao Han, Alibaba CloudLast year Alibaba T-Head reported that the basic features of Android had been ported onto RISC-V-based Xuantie cores. Since then more effort has been spent…
PolarFire® SoC FPGA in Conclusive RCHD-PF System Module | MicrochipOperational Technology (OT) and Transportation and Industrial Control Systems (ICS) are often forced to make concessions regarding security and updates to deliver critical functionality without…
DeepComputing and Xcalibyte Open Pre-Orders for First Native RISC-V Development Laptop; Quantities Limited | Xcalibyte and Deep ComputingROMA development platform features forthcoming quad-core RISC-V processor for fastest, seamless RISC-V software development experience. DeepComputing and Xcalibyte today opened pre-orders for the industry’s first…
SoC Design Challenge: the first engineering hackathon for students in Russia | Nickolay Ternovoy, SyntacoreYADRO and Syntacore hosted the first ever engineering hackathon for students in Russia. The event was organized in association with National Research University of Electronic…
Democratizing Chiplet-Based Processor Design | Ventana Micro SystemsBy Bob Wheeler, Principal Analyst, The Linley Group Chiplet-based designs promise reduced development costs and faster time to market, but they’ve been exclusive to large…
RISC-V Vector Processing is Taking Off | SiFiveThe RISC-V Vector Extension (RVV) Version 1.0 was ratified by RISC-V International in 2021. Since this public debut, there has been growing excitement about vector…
GreenWaves will Demonstrate Live the Ground-breaking AI and DSP Demos on its Ultra Low Power Chip at Embedded World 2022 | GreenWaves TechnologiesLocated in the micro-and nano-electronics hotspot of Grenoble, GreenWaves is a fabless semiconductor startup that designs and brings to market advanced ultra-low-power AI and DSP…
New RISC-V Innovations Lead AI to Open StandardIf the growing number of new RISC-V announcements aren’t enough proof of the license-free protocol’s momentum, there is a mountain of analyst predictions, trend research,…
[VIDEO] Join us for This Year’s RISC-V SummitFrom the IoT edge to the depths of space, RISC-V enables groundbreaking innovations. Join us at the RISC-V Summit 2024, October 22–23, at the Santa…
SEALSQ introduces new RISC-V secure hardware platform for IoT securityWith the need for more robust, quantum-resilient security the company’s new platform represents a significant advancement in securing critical data and infrastructure against the threats…
DeepComputing Announces the Launch of the DC-ROMA RISC-V Pad II!DeepComputing is excited to announce the official launch of the DC-ROMA RISC-V Pad II, a groundbreaking product designed to empower the RISC-V community with an advanced…
Microchip unveils PIC64 family of RISC-V multicore processor chips for Earth and for spaceLiterally the day after writing the article about the Microchip PolarFire SoC Discovery Kit based on the company’s PolarFire SoC FPGA, Microchip gave me a…
[VIDEO] Checking Out The Teensy Tiny RISC-V NanoKVM!Wendell checks out the NanoKVM. It's so tiny! Check it out here: https://sipeed.com/nanokvm Watch the video.
Harnessing power of RISC-V, Generative AI: Expert hardware security architect Avani Dave’s visionThe convergence of RISC-V architecture and generative AI is paving the way for revolutionary advancements in hardware security. These technologies promise to enhance the resilience…
RISC-V cluster IP for data centre SoCs and chipletsCalled P870-D, it is an update of the non-data centre P870, with support added for AMBA CHI protocol. “By harnessing a standard CHI bus,” said…
SiFive moves into RISC-V datacentre AI processor IPSiFive has modified its high end RISC-V core for more scalability in datacentre AI chip designs. The P870-D datacentre RISC-V IP is a variant of…
Akeana exits stealth mode with comprehensive RISC-V processor portfolioWith the support from A-list investors including Kleiner Perkins, Mayfield, and Fidelity the company has announced the formal availability of its expansive line of IP…
SiFive Announces New High-performance RISC-V Datacenter Processor for Demanding AI WorkloadsSanta Clara, Calif., Aug. 14, 2024 – Today SiFive, Inc., the gold standard for RISC-V computing, announced its new SiFive PerformanceTM P870-D datacenter processor to meet…