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Ashling RiscFree™ C/C++ SDK support for the Zephyr Real-Time Operating System (RTOS) Blog

Ashling RiscFree™ C/C++ SDK support for the Zephyr Real-Time Operating System (RTOS)

By Hugh O’Keeffe, Ashling Ashling’s RiscFree SDK provides full support for the  Zephyr RTOS running…

RISC-V Community NewsJuly 24, 2023

The Power of RISC-V: DAC Panel with Intel, Imperas, Meta, OpenHW Group & Ventana Blog

The Power of RISC-V: DAC Panel with Intel, Imperas, Meta, OpenHW Group & Ventana

RISC-V was one of the key themes at DAC 2023. We had a RISC-V Zone…

RISC-V Community NewsJuly 20, 2023

The Growing Momentum of RISC-V in Europe Blog

The Growing Momentum of RISC-V in Europe

By: Kezia Leung The RISC-V Summit Europe brought together members of the RISC-V community from…

RISC-V Community NewsJuly 19, 2023

YOLOX for Object Detection Blog

YOLOX for Object Detection

Author: Meng Chang This topic presents an example about how to deploy a YOLOX model…

RISC-V Community NewsJuly 19, 2023

SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V Ecosystem Blog

SiFive’s WorldGuard Security Platform Now Available to the Entire RISC-V Ecosystem

Data and codes are only as powerful as the security platform that protects them. Without…

RISC-V Community NewsJuly 19, 2023

Ashling announces RiscFree™ C/C++ SDK support for Lattice RISC-V MCU CPU Soft IP Cores Blog

Ashling announces RiscFree™ C/C++ SDK support for Lattice RISC-V MCU CPU Soft IP Cores

Limerick, Ireland – July 14, 2023 – Ashling today announced its RiscFree SDK has been…

RISC-V Community NewsJuly 14, 2023

The Incredible Growth of RISC-V in India Blog

The Incredible Growth of RISC-V in India

RISC-V is being adopted around the world as the silicon industry looks to the open…

RISC-V Community NewsJuly 13, 2023

Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR Core Blog

Open Source and CI-driven RTL Testing and Verification for Caliptra’s RISC-V VeeR Core

As part of CHIPS Alliance’s mission to enable a software-driven approach to silicon, working with Google…

AntmicroJuly 11, 2023

RISC-V Summit Europe 2023: Highlights from Barcelona Blog

RISC-V Summit Europe 2023: Highlights from Barcelona

More than 500 attendees, from across the world, attended the first-ever RISC-V Summit Europe Last…

RISC-V Community NewsJuly 6, 2023

The Call for Papers for RISC-V Summit China 2023 is Open Blog

The Call for Papers for RISC-V Summit China 2023 is Open

RISC-V Summit China is a major international event to share technical and business innovation around…

RISC-V Community NewsJune 28, 2023

GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations Blog

GreenRio: A Linux-Compatible RISC-V Processor Designed for Open-Source EDA Implementations

Since 20 years ago, Intel has successfully developed the 3 GHz processor in 130nm process.…

RISC-V Community NewsJune 25, 2023

Addition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC Core Blog

Addition of Single Precision Floating Point (F) extension in NucleusRV: RISC-V based RV32-IMC Core

Linux Foundation Mentorship Spring 2023 at Micro Electronics Research Lab (MERL) sponsored by RISC-V International…

helenJune 22, 2023

When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovation Blog

When tapas meet tech: Barcelona’s RISC-V Summit feeds our appetite for innovation

By Brett Cline, Codasip Alright, let's talk about Barcelona. Now, you might be thinking of…

anishaJune 19, 2023

Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced Functionality Blog

Integrating Tile Link UH in the Caravan Framework: A Journey of Enhanced Functionality

We are thrilled to share the details of our recent project, where we successfully integrated…

helenJune 14, 2023

Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPU Blog

Safety Critical Real-Time Operating System, SAFERTOS® Available With MiV_RV32 Soft CPU

SAFERTOS® is a real-time operating system (RTOS) designed specifically for use in safety-critical systems. WITTENSTEIN…

RISC-V Community NewsJune 7, 2023

SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer Box Blog

SOPHGO Donates 50 RISC-V Motherboards – Learn More About the Pioneer Box

New RISC-V International member SOPHGO is committed to the development and promotion of AI RISC-V…

RISC-V Community NewsJune 5, 2023

NOEL-V Processor’s Security Extensions for Safe and Secure Computing Blog

NOEL-V Processor’s Security Extensions for Safe and Secure Computing

Safety and security are increasingly important aspects when designing computer systems, and work is carried…

RISC-V Community NewsJune 1, 2023

NOEL-V: A RISC-V Processor for High-Performance Space Applications Blog

NOEL-V: A RISC-V Processor for High-Performance Space Applications

Space applications pose significant challenges for electronic systems as they must contend with a myriad…

RISC-V Community NewsMay 25, 2023

RISC-V: An Open Standard Instruction Set Architecture Blog

RISC-V: An Open Standard Instruction Set Architecture

By Mark Himelstein, CTO of RISC-V International In this blog post, we’ll explain why RISC-V…

Mark HimelsteinMay 24, 2023

RISC-V Announces Agenda for 2023 RISC-V Summit Europe Blog

RISC-V Announces Agenda for 2023 RISC-V Summit Europe

The first-ever RISC-V Summit Europe includes keynotes, technical talks, working groups, poster sessions, networking opportunities,…

RISC-V Community NewsMay 22, 2023

RISC-V and the Future of Machine Learning Computing Blog

RISC-V and the Future of Machine Learning Computing

By: Charlie Cheng, Managing Director of Polyhedron LLC Andes Technology Corp. was founded in 2004…

RISC-V Community NewsMay 22, 2023

Co-developing RISC-V AI solutions using Vector Extensions in Renode with Kenning Blog

Co-developing RISC-V AI solutions using Vector Extensions in Renode with Kenning

Kenning helps develop real-world Machine Learning solutions for ARM and RISC-V platforms such as NVIDIA…

AntmicroMay 18, 2023

T-Head Prototypes Innovative Hardware Support for Virtual IOMMU Blog

T-Head Prototypes Innovative Hardware Support for Virtual IOMMU

Author: Chong Ren Recently, T-Head has completed the QEMU-based proof-of-concept of hardware support for virtual…

RISC-V Community NewsMay 18, 2023

[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023 Blog

[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023

Calista Redmond talks with John Furrier & Rob Strechay at Open Source Summit NA 2023…

RISC-V Community NewsMay 15, 2023

How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti Picus Blog

How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti Picus

The RISC-V Golden model, also called the Sail model, defines the instruction execution of the…

RISC-V Community NewsMay 15, 2023