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Aion Silicon wins $12M deal for RISC-V HPC, AI design work
RISC-V Turns 15 With Fast Global Adoption
Latest Semidynamics IP Redefines Heterogeneous Compute with RISC-V
15 Years of Lauterbach & RISC-V: Enabling Great Chips, Superb IP and Future-proven Applications
The RISC-V World Sees Changes, Milestones, and Innovations
Boosting RISC-V SoC performance for AI and ML applications
Andrea Gallo Takes Over as RISC-V International’s New CEO
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
High RISC, High Reward: RISC-V at 15
RISC-V Technology Seeing Growing Maturity and Penetration
Automotive Industry Charts New Course with RISC-V
The RISC-V Foundation Appoints Calista Redmond As Chief Executive OfficerRISC-V International Statement on Spectre and Meltdown (2018)
Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse Adoptium
Empower Innovation with Numato Lab’s EagleCore™ PolarFire® SoC FPGA SOMMontaVista Software: Carrier Grade eXpress (CGX) 4.0 on Microchip PolarFire® SoC FPGA
Ensuring Integrity: The Role of SoC Security in Today’s Digital World
BRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPC
Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training PartnerIntroducing the RISC-V Enterprise Software Ecosystem Dashboard
Securing software execution with CHERI on a Codasip A730 RISC-V core
SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 Certification
Adding Physical Memory Protection to the VeeR EL2 RISC-V Core
Spotlighting Women in the Global RISC-V Community this International Women’s DaySoccer, Chips, RISC-V and Brazil
Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse AdoptiumEmpower Innovation with Numato Lab’s EagleCore™ PolarFire® SoC FPGA SOMMontaVista Software: Carrier Grade eXpress (CGX) 4.0 on Microchip PolarFire® SoC FPGAEnsuring Integrity: The Role of SoC Security in Today’s Digital WorldBRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPCAdvanced RISC-V Training Course | Maven Silicon – RISC-V Global Training PartnerIntroducing the RISC-V Enterprise Software Ecosystem DashboardSecuring software execution with CHERI on a Codasip A730 RISC-V coreSiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 CertificationAdding Physical Memory Protection to the VeeR EL2 RISC-V CoreSpotlighting Women in the Global RISC-V Community this International Women’s DaySoccer, Chips, RISC-V and Brazil
A 32-bit RISC-V processor made using molybdenum disulfide instead of silicon
[VIDEO] Canonical x Rivos: Delivering scalable RISC-V solutions in Data Centers
Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space Applications
2025 RISC-V CON: Andes Technology Celebrates 20 Years, Bringing Together Innovators, Engineers, and Ecosystem Leaders
Frontgrade Gaisler to commercialise neuromorphic AI for space
LDRA Updates Tools to Automate Worst-Case Execution Time Analysis for RISC-V
Angelina Jolie Was Right About Computers
Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platforms
Andes Technology Demo of Its RISC-V IP in a Spherical Image Processor and Meta’s AI Accelerator
Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit core
Security digital twin for RISC-V space chip
Aion Silicon wins $12M deal for RISC-V HPC, AI design workEnd-to-end ASIC partnership to accelerate global supercomputing market with open-standard, energy-efficient silicon. Aion Silicon announced it has secured a $12 million engagement to provide comprehensive design services for…
RISC-V Turns 15 With Fast Global AdoptionIn 2010, a modest summer project at UC Berkeley sought a suitable instruction set architecture (ISA). Now, 15 years later, RISC-V is a global alternative…
Latest Semidynamics IP Redefines Heterogeneous Compute with RISC-VVolker H. Politz, Chief Sales Officer at Semidynamics, explains why the company's Cervell™ All-in-One IP is so much more than an NPU. Remember when everyone…
15 Years of Lauterbach & RISC-V: Enabling Great Chips, Superb IP and Future-proven ApplicationsLauterbach is not only the global market leader in development tools for embedded systems; it has been part of the RISC-V community from the very…
The RISC-V World Sees Changes, Milestones, and InnovationsIt’s been a year of change so far for the RISC-V movement, from new leadership to an outpouring of hardware. In fifteen years, RISC-V has…
Boosting RISC-V SoC performance for AI and ML applicationsToday’s system-on-chip (SoC) designs integrate unprecedented numbers of diverse IP cores, from general-purpose CPUs to specialized hardware accelerators, including neural processing units (NPUs), tensor processors,…
Andrea Gallo Takes Over as RISC-V International’s New CEORISC-V International has announced Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since…
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-VDeveloper preview of Red Hat Enterprise Linux 10 on SiFive HiFive Premier P550 platform provides developers with a platform to optimize a new class of…
High RISC, High Reward: RISC-V at 15As RISC-V turns 15, we explore how a summer grad project became the official compute architecture of nations – and why its story is just…
RISC-V Technology Seeing Growing Maturity and PenetrationAt last month’s Andes Technology RISC-V Con event in San Jose, CA, the company announced a number of partnerships with companies like Imagination Technologies, Baya…
Automotive Industry Charts New Course with RISC-VThe European automotive industry, historically characterized by long development cycles and a complex, somewhat insulated ecosystem, is fundamentally transforming, and RISC-V is rising as a…
The RISC-V Foundation Appoints Calista Redmond As Chief Executive OfficerRedmond joins the RISC-V Foundation from IBM to continue to grow RISC-V membership, community engagement and market adoption The RISC-V Foundation, a non-profit corporation controlled by…
RISC-V International Statement on Spectre and Meltdown (2018)This statement was issued in 2018, and remains accurate today. Recent articles in the media have raised awareness around the processor security vulnerabilities named Meltdown and Spectre. These vulnerabilities are…
Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse AdoptiumExciting news for developers and enthusiasts in the software development world! Java versions 21 and 22 are now officially supported on the RISC-V architecture, thanks…
Empower Innovation with Numato Lab’s EagleCore™ PolarFire® SoC FPGA SOMBy: Samuel M, Global Marketing Manager at Numato Lab Developers who have struggled with limited computing power will now be able to harness their full…
MontaVista Software: Carrier Grade eXpress (CGX) 4.0 on Microchip PolarFire® SoC FPGABy: Iisko Lappalainen, Director of Product Management and Solutions at MontaVista Software Companies who have struggled with finding a stable, secure and highly configurable platform…
Ensuring Integrity: The Role of SoC Security in Today’s Digital WorldBy: Rob Fisher In an era where our lives are increasingly reliant on digital technologies, the security of system-on-chip (SoC) devices has emerged as a…
BRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPCAn international collaboration will enable Brazil to develop RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing in the country.…
Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training PartnerBy Sivakumar P R In this video, our Founder and CEO, Mr. P R Sivakumar, explains how he has authored the new RISC-V training course…
Introducing the RISC-V Enterprise Software Ecosystem DashboardAuthor: Isaac Chute, Director of Software Ecosystem, RISC-V International Historically there have been many iterations of compute platforms, such as Alpha, Vax, Solaris, PA-RISC, x86,…
Securing software execution with CHERI on a Codasip A730 RISC-V coreAuthor: Roddy Urquhart, Sr Technical Marketing Director, Codasip Introducing CHERI With cyber-attacks on systems growing in frequency and sophistication it is essential to improve the…
SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 CertificationSecuring your vehicle used to mean remembering to lock your doors at night and hiding your belongings under the seat when parked in public lots.…
Adding Physical Memory Protection to the VeeR EL2 RISC-V CoreAntmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure…
Spotlighting Women in the Global RISC-V Community this International Women’s DayInternational Women's Day, celebrated annually on March 8, recognizes the remarkable achievements of women across the globe. It is an important day to acknowledge the…
Soccer, Chips, RISC-V and BrazilBrazil Joins RISC-V International as Premier Member In the realm of global sports, soccer stands unparalleled, symbolizing not just a game but a tapestry of…
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Java 21 and 22 Now Available on RISC-V: A Collaboration Between RISE and Eclipse AdoptiumExciting news for developers and enthusiasts in the software development world! Java versions 21 and 22 are now officially supported on the RISC-V architecture, thanks…
Empower Innovation with Numato Lab’s EagleCore™ PolarFire® SoC FPGA SOMBy: Samuel M, Global Marketing Manager at Numato Lab Developers who have struggled with limited computing power will now be able to harness their full…
MontaVista Software: Carrier Grade eXpress (CGX) 4.0 on Microchip PolarFire® SoC FPGABy: Iisko Lappalainen, Director of Product Management and Solutions at MontaVista Software Companies who have struggled with finding a stable, secure and highly configurable platform…
Ensuring Integrity: The Role of SoC Security in Today’s Digital WorldBy: Rob Fisher In an era where our lives are increasingly reliant on digital technologies, the security of system-on-chip (SoC) devices has emerged as a…
BRAZIL AND EUROPE SIGN INNOVATIVE PROJECT WITH RISC-V TECHNOLOGY FOR HPCAn international collaboration will enable Brazil to develop RISC-V technologies to accelerate research and development in the areas of semiconductors and supercomputing in the country.…
Advanced RISC-V Training Course | Maven Silicon – RISC-V Global Training PartnerBy Sivakumar P R In this video, our Founder and CEO, Mr. P R Sivakumar, explains how he has authored the new RISC-V training course…
Introducing the RISC-V Enterprise Software Ecosystem DashboardAuthor: Isaac Chute, Director of Software Ecosystem, RISC-V International Historically there have been many iterations of compute platforms, such as Alpha, Vax, Solaris, PA-RISC, x86,…
Securing software execution with CHERI on a Codasip A730 RISC-V coreAuthor: Roddy Urquhart, Sr Technical Marketing Director, Codasip Introducing CHERI With cyber-attacks on systems growing in frequency and sophistication it is essential to improve the…
SiFive Upgrades Automotive Security for the RISC-V Ecosystem with New ISO/SAE 21434 CertificationSecuring your vehicle used to mean remembering to lock your doors at night and hiding your belongings under the seat when parked in public lots.…
Adding Physical Memory Protection to the VeeR EL2 RISC-V CoreAntmicro’s work with CHIPS Alliance’s Caliptra Root of Trust project, led by Google, AMD, NVIDIA, and Microsoft focuses around providing automated testing and verification infrastructure…
Spotlighting Women in the Global RISC-V Community this International Women’s DayInternational Women's Day, celebrated annually on March 8, recognizes the remarkable achievements of women across the globe. It is an important day to acknowledge the…
Soccer, Chips, RISC-V and BrazilBrazil Joins RISC-V International as Premier Member In the realm of global sports, soccer stands unparalleled, symbolizing not just a game but a tapestry of…
A 32-bit RISC-V processor made using molybdenum disulfide instead of siliconA team of engineers at Fudan University has successfully designed, built and run a 32-bit RISC-V microprocessor that uses molybdenum disulfide instead of silicon as…
[VIDEO] Canonical x Rivos: Delivering scalable RISC-V solutions in Data CentersRivos and Canonical have partnered to enhance RISC-V-readiness in Ubuntu for Data Centers, creating a streamlined and optimized Linux experience, specifically designed for Rivos platforms.…
Frontgrade Gaisler Launches New GRAIN Line and Wins SNSA Contract to Commercialize First Energy-Efficient Neuromorphic AI for Space ApplicationsGothenburg, Sweden (April 2, 2025) – The Swedish National Space Agency (SNSA) has awarded Frontgrade Gaisler, a leading provider of radiation-hardened microprocessors for space missions, a contract…
2025 RISC-V CON: Andes Technology Celebrates 20 Years, Bringing Together Innovators, Engineers, and Ecosystem LeadersSan Jose, CA, April 02, 2025 (GLOBE NEWSWIRE) -- Andes Technology, a leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and a Founding Premier…
Frontgrade Gaisler to commercialise neuromorphic AI for spaceThe Swedish National Space Agency (SNSA) has awarded Frontgrade Gaisler, a leading provider of radiation-hardened microprocessors for space missions, a contract to commercialise the first…
LDRA Updates Tools to Automate Worst-Case Execution Time Analysis for RISC-VThe tool suite automatically analyzes shared memory and measures worst-case execution time to ensure deterministic execution time for RISC-V processors. Developers working on real-time and…
Angelina Jolie Was Right About ComputersIncredibly, Angelina Jolie called it. The year was 1995. Picture Jolie, short of both hair and acting experience, as a teenage hacker in Hackers. Not a lot…
Rivos and Canonical partner to deliver scalable RISC-V solutions in Data Centers and enable an enterprise-grade Ubuntu experience across Rivos platformsThis blog looks at the benefit of Rivos and Canonical partnering and how this partnership will impact future AI and Data Analytics use cases. Artificial…
Andes Technology Demo of Its RISC-V IP in a Spherical Image Processor and Meta’s AI AcceleratorMarc Evans, Director of Business Development and Marketing at Andes Technology, demonstrates the company’s latest edge AI and vision technologies and products at the March…
Design and implementation of a hardened cryptographic coprocessor for a RISC-V 128-bit coreCryptography is a way of encoding and decoding information to guarantee its confidentiality and protection from unauthorised individuals. Within the realm of digital security and…
Security digital twin for RISC-V space chipUK defence contractor BAE Systems is using a security digital twin of a RISC-V processor from SiFive for a radiation hardened chip for space applications.…