RISC-V Workshop Zurich Proceedings

June 11-13, 2019

The RISC-V Workshop Zurich took place from Tuesday, June 11 to Thursday, June 13, 2019 at ETH Zurich in Zurich, Switzerland. The RISC-V Workshop Zurich showcased the open, expansive and international RISC-V ecosystem, highlighting current and prospective projects and implementations that influence the future evolution of the RISC-V instruction set architecture (ISA), with a focus on the momentum and growth of the RISC-V ecosystem across Europe and beyond. The event featured a variety of speaking sessions, along with poster presentations and demonstrations. RISC-V Foundation member companies exhibiting at the Workshop include: Antmicro, AdaCore, Calligo Technologies, Gowin, GreenWaves Technologies, IAR Systems, Imperas, Inno Logic, QuickLogic, SiFive, Syntacore, UltraSoC, Valtrix Systems, Western Digital and WolfSSL.

Proceedings

Check out the slides and videos from each of the sessions below.

Tuesday, June 11, 2019 RISC-V Workshop Zurich

Time	Event	Speaker, Affiliation	Slides
8:00	Registration & Networking
9:00	Guiding the Future of RISC-V	Calista Redmond, RISC-V Foundation	Slides \| Video
9:15	Energy efficient computing from Exascale to MicroWatts: The RISC-V playground	Luca Benini, ETH Zurich	Slides \| Video
9:40	RISC-V State of the Union	Krste Asanovic, UC Berkeley / SiFive	Slides \| Video
10:05	RISC-V Technical Committee Update	Silviu Chiricescu, Draper	Slides
10:20	RISC-V Marketing Committee Updates	Ted Marena, RISC-V Foundation	Slides \| Video
10:35	Networking Break
11:05	OpenHW Group Announces CORE-V Family of Open-Source RISC-V Cores	Rick O’Connor, OpenHW Group	Slides \| Video
11:30	OpenPiton+Ariane: The First Linux-Booting Open-Source RISC-V Manycore	Jonathan Balkind, Princeton University; Michael Schaffner, ETH Zurich	Slides \| Video
11:45	efabless’ Raven: PicoRV32 on an ASIC, Open Source, Open Silicon	Tim Edwards and Mohamed Kassem, efabless	Slides \| Video
12:00	PULP-NN: An Open-Source Library for Deeply-Embedded and Quantized Neural Networks (QNNs) on a RISC-V Based Parallel Ultra Low Power Cluster	Angelo Garofalo, University of Bologna; Luca Benini, ETH Zurich	Slides \| Video
12:15	Bit by bit – How to fit 8 RISC-V cores in a $38 FPGA board	Olof Kindgren, Qamcom Research & Technology	Slides \| Video
12:30	Networking Lunch & Table Tops Visit
13:30	OpenSBI Deep Dive	Anup Patel, Western Digital	Slides \| Video
13:55	Secure Bootloader for RISC-V	David Garske and Daniele Lacamera, wolfSSL, Inc.	Slides
14:10	An Open Source Approach to System Security	Helena Handschuh, Rambus	Slides \| Video
14:25	60 Second Poster Preview Sessions		Slides \| Video
14:50	Networking Break
15:20	PolarFire SoC: A Secure, Low Latency Heterogeneous Compute Platform for the Edge	Ted Speers, RISC-V Foundation \| Microchip Technology	Slides \| Video
15:45	CHIPS Alliance – An Open Hardware Group	Ted Marena, RISC-V Foundation \| Western Digital	Slides \| Video
16:00	PULP Platform: What’s next?	Frank Gürkaynak, ETH Zurich	Slides \| Video
16:15	Bridging the Gap in the RISC-V Memory Models	Stefanos Kaxiras, Uppsala University and Eta Scale AB; Alberto Ros, University of Marcia and Eta Scale AB	Slides \| Video
16:30	The first space-qualified Klessydra RISCV microcontroller to be launched on a satellite	Mauro Olivieri, Sapienza University of Rome and Visiting Researcher at Barcelona Supercomputing Center; Luigi Blasi and Francesco Vigli, Sapienza University of Rome	Slides \| Video
16:45	What You Simulate Is What You Synthesize: Design of a RISC-V Core from C++ Specifications	Simon Rokicki and Olivier Sentieys, INRIA	Slides \| Video
17:00	Better Living Through Bit Manipulation: Higher Performance at Lower Power	Clifford Wolf, Symbiotic EDA	Slides \| Video
17:15	Status Update of RISC-V P Extension Task Group	Chuanhua Chang, Andes Technology	Slides \| Video
17:30	Crypto Currently: The state of the Cryptographic Extensions and the challenges we face	Ken Dockser, Qualcomm	Slides \| Video
17:45	Vector Extension 0.7	Krste Asanovic, UC Berkeley \| SiFive	Slides \| Video
18:00	Networking Reception		Slides

Tuesday, June 12, 2019 RISC-V Workshop Zurich

Time	Event	Speaker, Affiliation	Slides
8:00	Network & Registration
9:00	RISC-V Software State of the Union	Palmer Dabbelt, SiFive	Slides\| Video
9:25	Embench TM: A Free Benchmark Suite for Embedded Computing from an Academic-Industry Cooperative (Towards the Long Overdue and Deserved Demise of Dhrystone)	David Patterson, RISC-V Foundation; Jeremy Bennett, Embecosm	Slides \| Video
9:50	Open Source Compiler Tool Chains and Operating Systems for RISC-V	Jeremy Bennett and Mark Corbin, Embecosm	Slides \| Video
10:15	Enabling RISC-V Development with QEMU	Alistair Francis, Western Digital	Slides \| Video
10:30	Networking Break
11:00	Building Better Soft RISC-V IP Cores through Mi-V verification and compliance Testing	Stuart Hoad, Microchip Technology	Slides \| Video
11:25	Developing with FreeRTOS and RISC-V	Richard Barry, AWS	Slides \| Video
11:50	Enable RISC-V capability in cloud computing	Zhipeng Huang, Huawei	Slides \| Video
12:05	Networking Lunch and Table Top Visits
13:05	SweRV (RISC-V) Debug, Trace and On-chip Analytics for SOC	Rao Bommana and Mukesh Panda, Western Digital	Slides
13:20	TestRIG: Using RVFI-DII to eliminate the “Test gap” between specification and implementation	Jonathan Woodruff, University of Cambridge	Slides \| Video
13:35	Formal Verification of PULPino and other RISC-V SoCs	Nicolae Tusinchi and Sven Beyer, OneSpin Solutions	Slides
13:50	Ada & PolarFire SoC, a software and hardware alloy for Safety & Security	Fabien Chouteau, AdaCore; Pierre Selwan, Microsemi	Slides \| Video
14:05	Building Secure Systems using RISC-V and Rust	Arun Thomas, Draper Labs	Slides \| Video
14:20	60 Second Poster Preview Sessions		Slides \| Video
14:50	Networking Break
15:20	An open-source API proposal for a multi-domain RISC-V Trusted Execution Environment	Cesare Garlati, Hex Five Security	Slides \| Video
15:45	Protecting RISC-V Processors against Physical Attacks	Mario Werner and Robert Schilling, Graz University of Technology	Slides \| Video
16:00	A Security Policy Definition Language, Semantics, and Open Source Tools	Greg Sullivan, Dover Microsystems; Chris Casinghino, Draper	Slides \| Video
16:15	An Intrinsically Secure RISC V processor	Olivier Savry, CEA	Slides \| Video
16:30	SiFive 7-series RISC-V Core IP Enables Embedded Intelligence	James Prior, SiFive	Slides
16:45	CloudBEAR RISC-V Processor IP Product Line	Alexander Kozlov, CloudBEAR	Slides \| Video
17:00	Syntacore 64bit RISC-V core IP product line	Alexander Redkin and Dmitry Gusev, Syntacore	Slides \| Video
17:15	Configurable LLDB Debuggers for RISC-V	Zdenek Prikryl, Codasip	Slides \| Video
18:00	RISC-V Foundation Members Dinner

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RISC-V Workshop Zurich Proceedings