7 Things I Learned at RISC-V Summit North America 2025
As the dust settles on RISC-V Summit North America 2025, Tom Gall looks back at what he learned at his first RISC-V Summit since joining as VP of Technology.
ChannelLife: Edge AI, security & RISC-V to redefine IoT chips by 2026Channel Life: The IoT semiconductor market is heading into a major shift by 2026, driven by the mainstream adoption of edge AI, the rise of…
Electronic Design: Checking Out the RISC-V Summit North America 2025Electronic Design: Although the RISC-V Summit North America 2025 has concluded, viewers can still explore many of the keynotes and sessions now available online. William…
Semiconductor Engineering: Why Openness Matters For AI At The EdgeSemiconductor Engineering: AI continues to migrate towards the edge and is no longer confined to the data center. Edge AI brings several key advantages, delivering…
Enabling High Performance RISC-V Software for AI in the Real WorldEmbecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
Andes: d-Matrix and Andes Team on World’s Highest Performing, Most Efficient Accelerator for AI Inference at ScaleAndes: d-Matrix and Andes have partnered to integrate Andes’ high-performance AX46MPV RISC-V CPU IP into d-Matrix’s next-generation Raptor accelerator, the first to feature 3D In-Memory…
EDN: RISC-V Summit spurs new round of automotive supportEDN: RISC-V adoption in automotive applications is accelerating, with new partnerships and certified processor cores enabling software-defined vehicles and safety-critical systems. Collaborations among Quintauris, Andes,…
WebProNews: RISC-V’s ISO Milestone: Open ISA Poised for Global DominanceWebProNews: RISC-V International has achieved Publicly Available Specification (PAS) Submitter status from ISO/IEC JTC1, marking a major step toward international standardization of its open instruction…
We’re Showcasing RISC-V at SC25, the World’s Largest Supercomputing ConferenceI’m heading to SC25 in St. Louis next week to advocate for the growing role of RISC-V in high-performance computing (HPC), alongside my peers in…
EEWorldOnline: MIPS releases multithreaded processor for edge computingEEWorldOnline: MIPS has begun sampling its new I8500 processor, a scalable, multithreaded data movement processor IP designed for real-time, event-driven computing across hyperscale, automotive, industrial,…
EDN: The next RISC-V processor frontier: AIEDN: At RISC-V Summit North America 2025, industry leaders unveiled the latest advances in CPU cores, vector processors, and AI-powered designs shaping the next wave…
All About Circuits: Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold ComputingDeveloped with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors. In a…
EETimes: Google Open-Sources NPU IP, Synaptics Implements ItGoogle Research has open-sourced its Coral NPU IP (previously codenamed Kelvin), which it is giving to the industry in a bid to accelerate edge AI…
Introducing the RISCstar Toolchain for RISC-VThe newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter StatusAt RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded DevicesAt RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…
New Course Coming Soon: Porting Software to RISC-V (LFD 114)The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…
Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor ProjectThe eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…
Call for Proposals: AI-Driven Software Porting to RISC-VRisky Systems’ Bob Jones explains why the company’s latest core is set to revolutionize the AI SoC market, and how it intends to use it…
NASA, Google, AWS Join Stellar Line-up for RISC-V Summit North America 2025RISC-V Summit North America 2025 will bring the global RISC-V community together in Santa Clara for two days of keynotes, technical sessions, workshops, and demos.
RISC-V International Newsletter – July 2025A Note From Our CEO Welcome to the latest RISC-V newsletter, my first as the new CEO at RISC-V International. I’m incredibly excited to step…
Embedded Evolution: A New RISC-V CEO & AI-Powered PlatformsIn this episode of Embedded Insiders, we’re joined by RISC-V’s newest CEO, Andrea Gallo, who outlines his vision for the company’s future. From accelerating ecosystem growth…
High RISC, High Reward: RISC-V at 15As RISC-V turns 15, we explore how a summer grad project became the official compute architecture of nations – and why its story is just…
RISC-V International and the RISE Project Join Forces for Yocto Project SupportRISC-V International and the RISE Project are teaming up to participate in the Yocto Project. RISC-V International has upgraded from Silver to a Platinum membership…
RISC-V International Promotes Andrea Gallo to CEORISC-V International announces Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since June…
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ FlowVerification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
New to RISC-V? Here’s Why Summit 2025 is the Place to Begin Your JourneyThe 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
RISC-V: The AI-Native Platform for the Next Trillion Dollars of ComputeWe explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Design Approaches and Architectures of RISC-V SoCsAuthor: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
From Simulation Bottlenecks to Formal Confidence: Leveraging Formal for Exhaustive RISC-V VerificationIntroduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
Arteris’ Multi-Die Solution for the RISC-V Ecosystemby Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
7 Critical Components of the Car of TomorrowWith IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every…
RISC-V Summit China 2025: Reflections from a RISC-V Software ContributorBy Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
Certifying Embedded Applications Running on PolarFire® SoC FPGAsBy: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
Cost-Effective and Scalable: A Smarter Choice for RISC-V DevelopmentThe RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…
Enabling High Performance RISC-V Software for AI in the Real WorldEmbecosm used the oneAPI Construction Kit to explore accelerating PyTorch using RISC-V cores, trying over a thousand in emulation and some on an FPGA. This…
Optimizing Hardware for Neural Network Inference using Virtual PrototypesProject Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…
A RISC-V Based Accelerator for Post Quantum CryptographyProject Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware…
CVA6 RISC-V PMP Vulnerabilities against FIAProject Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering…
Learning Computer Architecture with a Visual Simulation of RISC-V ProcessorsProject Snapshot This work presents an interactive way of teaching computer architecture using Logisim Evolution, enabling students to construct and debug single-cycle and pipelined CPUs.…
TYRCA: A RISC-V Tightly-Coupled Accelerator For Code-Based CryptographyProject Snapshot Post-quantum cryptography (PQC) has garnered significant attention across various communities, particularly with the National Institute of Standards and Technology (NIST) advancing to the…
HaDes-V – Learning by Puzzling: A Modular Approach to RISC-V Processor Design EducationProject Snapshot HaDes-V is an Open Educational Resource for learning microcontroller design. It guides through creating a 5-stage pipelined 32-bit RISC-V processor using SystemVerilog and…
Simplifying Sail Simulations and Architectural Compatibility TestingGreg Sterling from RISC-V International has worked with Carl Perry to create a RISC-V development container to help streamline the process of working with RISC-V…
TestRIG – Randomized Testing of RISC-V CPUsTestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in…
Towards an Integrated Matrix Extension: Workload Analysis of CNN Inference with QEMU TCG PlugingsIntroduction Following the gap analysis done in the second half of 2023, the Vector Special Interest Group (SIG-Vector) has been working on specifying instructions to…
Longnail: Hardware Synthesis of CoreDSL Custom Instructions for MCU- and Application-Class CoresTammo Mürmann has just commenced his PhD studies at the Technical University of Darmstadt as part of the Embedded Systems and Applications Group (ESA). During…
How to Share Your Work and See What Others Are Building On RISC-VHello RISC-V Community, We’ve heard your feedback! Many of you expressed an interest in seeing RISC-V projects from around the world, as well as having…
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ FlowVerification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
New to RISC-V? Here’s Why Summit 2025 is the Place to Begin Your JourneyThe 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
RISC-V: The AI-Native Platform for the Next Trillion Dollars of ComputeWe explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Design Approaches and Architectures of RISC-V SoCsAuthor: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
From Simulation Bottlenecks to Formal Confidence: Leveraging Formal for Exhaustive RISC-V VerificationIntroduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
Arteris’ Multi-Die Solution for the RISC-V Ecosystemby Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
7 Critical Components of the Car of TomorrowWith IAA Mobility and the RISC-V Automotive Conference 2025 just around the corner, I’ve pulled together the top themes from recent expert panels that every…
RISC-V Summit China 2025: Reflections from a RISC-V Software ContributorBy Guodong Xu, Director China Operations, RISCstar Solutions The 2025 RISC-V Summit China reached an unprecedented level of excitement, drawing a record-breaking crowd of over…
Certifying Embedded Applications Running on PolarFire® SoC FPGAsBy: Stephen Di Camillo, Technical Marketing and Business Development Manager Embedded system developers facing the increasingly complex challenge of certifying embedded applications running on complex…
Cost-Effective and Scalable: A Smarter Choice for RISC-V DevelopmentThe RISC-V ecosystem is witnessing remarkable growth, driven by increasing industry adoption and a thriving open-source community. As companies and developers seek customizable computing solutions,…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing Libraries (Vectorization)By Zhanheng Yang, Alibaba DAMO Academy 1. Introduction In the previous article of the XuanTie Optimized Computing Libraries series, we provided a systematic overview of…
ChannelLife: Edge AI, security & RISC-V to redefine IoT chips by 2026Channel Life: The IoT semiconductor market is heading into a major shift by 2026, driven by the mainstream adoption of edge AI, the rise of…
Electronic Design: Checking Out the RISC-V Summit North America 2025Electronic Design: Although the RISC-V Summit North America 2025 has concluded, viewers can still explore many of the keynotes and sessions now available online. William…
Semiconductor Engineering: Why Openness Matters For AI At The EdgeSemiconductor Engineering: AI continues to migrate towards the edge and is no longer confined to the data center. Edge AI brings several key advantages, delivering…
Andes: d-Matrix and Andes Team on World’s Highest Performing, Most Efficient Accelerator for AI Inference at ScaleAndes: d-Matrix and Andes have partnered to integrate Andes’ high-performance AX46MPV RISC-V CPU IP into d-Matrix’s next-generation Raptor accelerator, the first to feature 3D In-Memory…
EDN: RISC-V Summit spurs new round of automotive supportEDN: RISC-V adoption in automotive applications is accelerating, with new partnerships and certified processor cores enabling software-defined vehicles and safety-critical systems. Collaborations among Quintauris, Andes,…
WebProNews: RISC-V’s ISO Milestone: Open ISA Poised for Global DominanceWebProNews: RISC-V International has achieved Publicly Available Specification (PAS) Submitter status from ISO/IEC JTC1, marking a major step toward international standardization of its open instruction…
EEWorldOnline: MIPS releases multithreaded processor for edge computingEEWorldOnline: MIPS has begun sampling its new I8500 processor, a scalable, multithreaded data movement processor IP designed for real-time, event-driven computing across hyperscale, automotive, industrial,…
EDN: The next RISC-V processor frontier: AIEDN: At RISC-V Summit North America 2025, industry leaders unveiled the latest advances in CPU cores, vector processors, and AI-powered designs shaping the next wave…
All About Circuits: Upbeat Technology’s RISC-V MCU Takes Flight With Near-Threshold ComputingDeveloped with SiFive, the dual-core SoC uses patented error correction to achieve a record 16.8 µW/MHz/DMIPS, targeting next-gen wearables, drones, and IoT sensors. In a…
EETimes: Google Open-Sources NPU IP, Synaptics Implements ItGoogle Research has open-sourced its Coral NPU IP (previously codenamed Kelvin), which it is giving to the industry in a bid to accelerate edge AI…
SemiWiki: Insights from the 2025 RISC-V Summits and Andes Technology’s Pivotal RoleAnnual RISC-V Summits, organized by RISC-V International, serve as vital hubs for innovation, writes SemiWiki's Daniel Nenni.
NewElectronics: RISC-V International to Announce 25% Market PenetrationRISC-V International is set to announce that silicon on the open-standard has reached 25% market penetration, according to research from SHD Group whose findings on…