RISC-V International Names Tom Gall as Vice President of Technology
Open-technology veteran Gall will drive RISC-V International’s technical vision and collaboration strategy, strengthening the organisation’s push for worldwide adoption of the RISC-V ISA.
Introducing the RISCstar Toolchain for RISC-VThe newly released RISCstar toolchain is a pre-compiled family of GNU toolchains for RISC-V developers. It supports the entire RISC-V ecosystem, from the latest 64-bit…
RISC-V Takes First Step Toward International Standardization as ISO/IEC JTC1 Grants PAS Submitter StatusAt RISC-V Summit North America 2025, Andrea Gallo, CEO RISC-V International, and Phil Wennblom, Chair of the ISO/IEC Joint Technical Committee (JTC 1)., announced that…
SemiWiki: Insights from the 2025 RISC-V Summits and Andes Technology’s Pivotal RoleAnnual RISC-V Summits, organized by RISC-V International, serve as vital hubs for innovation, writes SemiWiki's Daniel Nenni.
NewElectronics: RISC-V International to Announce 25% Market PenetrationRISC-V International is set to announce that silicon on the open-standard has reached 25% market penetration, according to research from SHD Group whose findings on…
Ashling and Embecosm Extend PyTorch AI to RISC-V Embedded DevicesAt RISC-V North American Summit in Santa Clara, Ashling and Embecosm today announced robust ExecuTorch implementations optimised for resource-constrained devices, including RISC-V based microcontrollers. The…
Optimizing Hardware for Neural Network Inference using Virtual PrototypesProject Snapshot Identifying the optimal hardware configuration for running NN inference on edge devices is critical for maximizing performance. Tailoring HW designs to specific applications…
New Course Coming Soon: Porting Software to RISC-V (LFD 114)The knowledge gap for porting software to RISC-V is about to close. RISCstar Solutions, in close collaboration with RISC-V International and the Linux Foundation, has…
Tom’s Hardware: Risc-V Set to Announce 25% Market PenetrationRISC-V International plans to announce that silicon on the open-standard has reached 25% market penetration later this month, says Tom's Hardware writer Sunny Grimm. Market…
EE Times: Why RISC-V + Blockchain Is the Conversation I’ve Been Waiting to HaveIn this article for EE Times, Daniela Barbosa, General Manager of Decentralized Technologies at the Linux Foundation and Executive Director of LF Decentralized Trust, argues…
Europe Achieves a Key Milestone with the Europe’s First Out-of-Order RISC-V Processor chip, with the eProcessor ProjectThe eProcessor Project today announced the successful development and deployment of the Europe’s first out-of-order RISC-V processor silicon. The processor, manufactured in a 22nm process,…
IoT Insider: Quintauris-Everspin Partnership Targets Dependable Open-standard Processors for Car IndustryQuintauris, the industry consortium set up to promote compatibility in RISC-V-based products, has formed a strategic partnership with US memory maker Everspin Technologies to strengthen the reliability…
A RISC-V Based Accelerator for Post Quantum CryptographyProject Snapshot Post-Quantum Cryptography (PQC) is a topic of increased interest in the past decade, both with regards to the cryptosystem definition and the hardware…
RISC-V International Newsletter – April 2025As we wrap up a busy Q1 for RISC-V, the excitement is building as RISC-V Summit Europe 2025 approaches, taking place from May 12-15 in…
RISC-V launches search for new CEO2024 was a year of accelerating momentum for RISC-V. Adoption grew across a diverse range of markets, the foundational new RVA23 Profile was ratified, and many new…
RISC-V International Newsletter – December 2024Message from RISC-V International As we reflect on 2024, we wanted to express our heartfelt gratitude to the entire RISC-V ecosystem. This year has been…
RISC-V CEO Calista Redmond resigns after 5+ years of progressBy: Calista Redmond | CEO, RISC-V International It is with deep gratitude that I announce my resignation from RISC-V International as I’ve accepted a new…
RISC-V Announces Ratification of the RVA23 Profile StandardVector and Hypervisor extensions are key mandatory components of the RVA23 Profile, addressing math-intensive workloads including AI/ML & cryptography, and enterprise hardware, operating systems and…
RISC-V International Newsletter – September 2024Message from RISC-V International The countdown is on! RISC-V Summit North America takes place on October 22-23 at the Santa Clara Convention Center. The Summit is…
RISC-V International Names Andrea Gallo as VP, TechnologyIndustry Veteran Brings Software and Hardware Experience to Role Guiding all RISC-V Technical Activities MUNICH, Germany – June 24, 2024 – RISC-V International, the global…
RISC-V International Newsletter – June 2024Message from RISC-V International Events are key to the success of RISC-V, where we come together to share the latest developments and build the relationships…
MEDIA ALERT: Calista Redmond, CEO of RISC-V International, to Speak at ESD Alliance 2024 CEO Executive OutlookMEDIA ALERT: Calista Redmond, CEO of RISC-V International, to Speak at ESD Alliance 2024 CEO Executive Outlook WHO: Calista Redmond, CEO of RISC-V International WHAT:…
RISC-V International Achieves Milestone with Ratification of 40 Specifications in Two YearsLatest Ratifications Primarily Target Core Areas of Efficiency, Vector, and Virtualization ZURICH – April 4, 2024 – RISC-V International, the global standards organization, today announced…
RISC-V International to Showcase the Latest RISC-V Developments at embedded world 2024WHO: RISC-V International WHAT: RISC-V International will be exhibiting at embedded world 2024, sharing the latest developments from its community and showcasing a range of…
RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip DesignersMaven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing LibrariesBy Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise in…
RISC-V International at Embedded World, 11-13th March, Nuremberg Germanyembedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany between 11-13…
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’sBuild safety-critical automotive, aeronautic, space, and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire FPGAs. By Evan Price, Sales…
Building on a Legacy of Security: Introducing Polar-VPXSundanceDSP, a leading provider of high-performance FPGA-based solutions, is proud to announce the latest addition to its product lineup: Polar-VPX. This cutting-edge 3U VPX form-factor…
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce RiskBy John Min John Min is VP of Customer Success at Arteris. He possesses architectural expertise that enables the successful management of design trade-offs…
How NVIDIA Shipped One Billion RISC-V Cores In 2024At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the…
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels…
RISC-V at Embedded World 2025: Innovation, Networking & Must-See SessionsThe RISC-V Pavilion returns to embedded world for 2025! Visit us in Hall 5, Stand 5-119, to discover the latest RISC-V technologies and applications and…
Accelerating RISC-V development with Tessent UltraSight-VBy: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early…
Chromium Performance Optimization on XuanTie RISC-V ProcessorsYang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode,…
Exploring RISC-V ISA Developments and Technical Highlights from 20242024 has been a year of great technical progress for the RISC-V ISA. Our 75 Committees and Groups, staffed by contributors from RISC-V member organizations…
Featured Work: Microarchitecture Security: The Spectre AffairAuthor: Ronan Lashermes, Hardware Security Research Engineer at Inria. Results from a joint work with Hery Andrianatrehina, Joseph Paturel, Simon Rokicki and Thomas Rubiano at…
RISC-V Powered Executive M.Tech VLSI PG Program for Next-Gen Chip DesignersMaven Silicon has collaborated with PES University and launched a unique Executive MTech in VLSI Design, Blended Weekend Classroom Degree Program for working professionals in India. This advanced…
Enhancing Commercial Software Adaptation with XuanTie Optimized Computing LibrariesBy Yunfei Zhou, Alibaba DAMO Academy 1. Introduction The RISC-V architecture has matured over time. Its open, flexible, and extensible nature shows great promise in…
RISC-V International at Embedded World, 11-13th March, Nuremberg Germanyembedded world, the leading trade show covering hardware, software, tools, and related services for the embedded systems market, took place in Nuremberg, Germany between 11-13…
CAST Provides a Functional Safety RISC-V Processor IP for the Microchip FPGA’sBuild safety-critical automotive, aeronautic, space, and other systems with the Functional Safety RISC-V Processor IP core from CAST and PolarFire FPGAs. By Evan Price, Sales…
Building on a Legacy of Security: Introducing Polar-VPXSundanceDSP, a leading provider of high-performance FPGA-based solutions, is proud to announce the latest addition to its product lineup: Polar-VPX. This cutting-edge 3U VPX form-factor…
Soft Tiling RISC-V Processor Clusters Speed Design and Reduce RiskBy John Min John Min is VP of Customer Success at Arteris. He possesses architectural expertise that enables the successful management of design trade-offs…
How NVIDIA Shipped One Billion RISC-V Cores In 2024At the recent RISC-V North America summit, NVIDIA’s Vice President of Multimedia Architecture, Frans Sijstermans gave his insight into why NVIDIA chose RISC-V as the…
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels…
RISC-V at Embedded World 2025: Innovation, Networking & Must-See SessionsThe RISC-V Pavilion returns to embedded world for 2025! Visit us in Hall 5, Stand 5-119, to discover the latest RISC-V technologies and applications and…
Accelerating RISC-V development with Tessent UltraSight-VBy: Francisca Tan, Product Management Lead – Tessent Embedded Analytics Siemens’ longstanding and deep engagement with the RISC-V community dates back to the foundation’s early…
Chromium Performance Optimization on XuanTie RISC-V ProcessorsYang Li, Alibaba DAMO Academy Chromium, the most widely adopted open-source browser engine, serves as the foundation for numerous mainstream applications, including Chrome, Electron, VSCode,…
Exploring RISC-V ISA Developments and Technical Highlights from 20242024 has been a year of great technical progress for the RISC-V ISA. Our 75 Committees and Groups, staffed by contributors from RISC-V member organizations…
Tom’s Hardware: Risc-V Set to Announce 25% Market PenetrationRISC-V International plans to announce that silicon on the open-standard has reached 25% market penetration later this month, says Tom's Hardware writer Sunny Grimm. Market…
EE Times: Why RISC-V + Blockchain Is the Conversation I’ve Been Waiting to HaveIn this article for EE Times, Daniela Barbosa, General Manager of Decentralized Technologies at the Linux Foundation and Executive Director of LF Decentralized Trust, argues…
IoT Insider: Quintauris-Everspin Partnership Targets Dependable Open-standard Processors for Car IndustryQuintauris, the industry consortium set up to promote compatibility in RISC-V-based products, has formed a strategic partnership with US memory maker Everspin Technologies to strengthen the reliability…
ElectroPages: RISC-V Acceleration for Deep Learning at the EdgeBy running an open-source NVIDIA Deep Learning Accelerator directly on a RISC-V chip (without a traditional operating system), a group of researchers has achieved impressive…
Jon Peddie Research: RISC-V’s New CEO Charts Path to Global AdoptionRISC-V International CEO Andrea Gallo outlines how RISC-V is accelerating across AI, automotive, data centers, and supercomputing.
22nm RISC-V AI Chip Targets Wearables and IoTEMASS has introduced the ECS-DoT, a 22nm microprocessor designed to bring milliWatt-scale intelligence directly to edge and IoT devices.
RISC-V: Shaping the Future of Mobility with Open StandardsThe automotive industry gathered last week in Munich to drive the future of mobility forward, with a particular focus on compute and software, two of…
Orange Pi RV2 $40 RISC-V SBC : Friendly Gateway to IoT and AI ProjectsWhat if you could explore the innovative world of RISC-V computing without breaking the bank? The Orange Pi RV2 promises exactly that, a budget-friendly gateway…
TechRadar: A Chip With ‘Thousands’ of RISC-V Cores Could Change the Way Servers Are DesignedAccording to Wayne Williams at TechRadar, a startup called XCENA has unveiled the MX1 chip featuring thousands of custom RISC‑V cores, leveraging CXL 3.2 and…
SiFive Expands Its RISC-V Intelligence Family To Address Exploding AI WorkloadsSiFive just announced an array of new additions to its product stack that run the gamut, from tiny, ultra lower-power designs for far edge IoT…
Quintauris and TASKING join forces to power RISC-V in automotiveQuintauris and TASKING have announced a new partnership to strengthen RISC-V development for the automotive industry. As part of this collaboration, Quintauris will integrate TASKING’s RISC-V compiler…
Microchip’s PolarFire® SoC FPGA Meets Beagle Board: High-Performance SoC with BeagleV®-FireThe BeagleV®-Fire board from BeagleBoard.org features Microchip’s PolarFire® SoCs, harnessing its RISC-V and FPGA technology, creating a powerful platform for innovation. As part of Microchip’s Mi-V ecosystem, it benefits from a rich set…