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ElectroPages: RISC-V Acceleration for Deep Learning at the Edge
Jon Peddie Research: RISC-V’s New CEO Charts Path to Global Adoption
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ Flow
New to RISC-V? Here’s Why Summit 2025 is the Place to Begin Your Journey
22nm RISC-V AI Chip Targets Wearables and IoT
Call for Proposals: AI-Driven Software Porting to RISC-V
RISC-V: Shaping the Future of Mobility with Open Standards
NASA, Google, AWS Join Stellar Line-up for RISC-V Summit North America 2025
Orange Pi RV2 $40 RISC-V SBC : Friendly Gateway to IoT and AI ProjectsKVM Forum 2025 | rust-vmm 社区 RISC-V 支持进展
TechRadar: A Chip With ‘Thousands’ of RISC-V Cores Could Change the Way Servers Are Designed
SiFive Expands Its RISC-V Intelligence Family To Address Exploding AI Workloads
RISC-V International Newsletter – March 2024
RISC-V International Newsletter – December 2023
RISC-V International Marks Banner Year for RISC-V Adoption, Technical Momentum, and Community EngagementRISC-V International Newsletter – November 2023RISC-V International Newsletter – September 2023
RISC-V International Newsletter – May/June 2023Ashling and Imagination announce Ashling’s RiscFree™ C/C++ SDK support for RISC-V-based Catapult family.
RISC-V Newsletter – March 2, 2023
First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across Industries
RISC-V Honors Outstanding Technical and Community Contributions for 2022RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in Market
RISC-V Global Summit Will Showcase Enormous Momentum for the Open Standard Hardware Architecture and Software Ecosystem | RISC-V International
RISC-V 2024: A Year of Global Growth and Innovation
S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC
My Journey with the RISC-V Mentorship | Sailing Downstream II
XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative Computing
Enhancing the Future of AI/ML with Attached Matrix Extension
Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career Pivot
Triton kernel performance on RISC-V CPU
Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMsStream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix Implementation
Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoT
RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source Innovations
Chile’s First Steps with RISC-V: Paving the Way for Technological Innovation
RISC-V 2024: A Year of Global Growth and InnovationS2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPCMy Journey with the RISC-V Mentorship | Sailing Downstream IIXuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative ComputingEnhancing the Future of AI/ML with Attached Matrix ExtensionMeet Andrea Gallo, RVFA: A Senior IT Leader’s Career PivotTriton kernel performance on RISC-V CPUStream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMsStream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix ImplementationReal-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoTRISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source InnovationsChile’s First Steps with RISC-V: Paving the Way for Technological Innovation
Leveraging Formal Verification to find critical RTL bugs in a RISC-V core – a LUBIS EDA best practice
RISC-V basics: The truth about custom extensions
EE Times: China Unyielding Ascent in RISC-V
Ashling Announces RiscFree™ Debug and Trace Support for Tenstorrent TT-Ascalon™ RISC-V CPUs
S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
Legendary GPU architect Raja Koduri’s new startup leverages RISC-V and targets CUDA workloads — Oxmiq Labs supports running Python-based CUDA applications unmodified on non-Nvidia hardware
Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous Missions
RISC-V’s Ascent Could Reshape The Global Compute Landscape
How Next-Gen Chips Are Unlocking RISC-V’s Customization Advantage
Nvidia to bring CUDA platform support to the RISC-V
Three high-performance RISC-V processors to watch in H2 2025: UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3
Breakthrough in Automotive AI: Running BEVFormer on SiFive’s Early Access RISC-V Intelligence XM Platform
ElectroPages: RISC-V Acceleration for Deep Learning at the EdgeBy running an open-source NVIDIA Deep Learning Accelerator directly on a RISC-V chip (without a traditional operating system), a group of researchers has achieved impressive…
Jon Peddie Research: RISC-V’s New CEO Charts Path to Global AdoptionRISC-V International CEO Andrea Gallo outlines how RISC-V is accelerating across AI, automotive, data centers, and supercomputing.
A Hands-On Look at RISC-V Verification for Next-Gen Designs Using Synopsys’ FlowVerification is no mean feat. With new extensions, evolving specs, growing pressure for faster cycles, and a continuous flow of tool innovations, it constantly balances…
New to RISC-V? Here’s Why Summit 2025 is the Place to Begin Your JourneyThe 2025 RISC-V Summit North America runs October 22–23 in Santa Clara, California, with a member day on October 21. If you are new to…
22nm RISC-V AI Chip Targets Wearables and IoTEMASS has introduced the ECS-DoT, a 22nm microprocessor designed to bring milliWatt-scale intelligence directly to edge and IoT devices.
Call for Proposals: AI-Driven Software Porting to RISC-VRisky Systems’ Bob Jones explains why the company’s latest core is set to revolutionize the AI SoC market, and how it intends to use it…
RISC-V: Shaping the Future of Mobility with Open StandardsThe automotive industry gathered last week in Munich to drive the future of mobility forward, with a particular focus on compute and software, two of…
NASA, Google, AWS Join Stellar Line-up for RISC-V Summit North America 2025RISC-V Summit North America 2025 will bring the global RISC-V community together in Santa Clara for two days of keynotes, technical sessions, workshops, and demos.
Orange Pi RV2 $40 RISC-V SBC : Friendly Gateway to IoT and AI ProjectsWhat if you could explore the innovative world of RISC-V computing without breaking the bank? The Orange Pi RV2 promises exactly that, a budget-friendly gateway…
KVM Forum 2025 | rust-vmm 社区 RISC-V 支持进展2025 年 9 月 3 日至 4 日，被誉为虚拟化领域里最具影响力的活动之一—— KVM Forum 在意大利米兰顺利举行。本次大会包括对 KVM 虚拟化软件栈最新进展的更新、面向未来的路线规划等议题；同时设有 BoF（Birds of a Feather）专题讨论，便于就关键方向与战略性决策开展深入对话。作为 KVM 社区的重要汇聚点，KVM Forum 促成内核、平台与应用实践者的高效沟通与协作。9 月 3 日下午两点，中国科学院软件研究所 OERV…
TechRadar: A Chip With ‘Thousands’ of RISC-V Cores Could Change the Way Servers Are DesignedAccording to Wayne Williams at TechRadar, a startup called XCENA has unveiled the MX1 chip featuring thousands of custom RISC‑V cores, leveraging CXL 3.2 and…
SiFive Expands Its RISC-V Intelligence Family To Address Exploding AI WorkloadsSiFive just announced an array of new additions to its product stack that run the gamut, from tiny, ultra lower-power designs for far edge IoT…
RISC-V International Newsletter – March 2024Message from RISC-V International 2024 is now well underway and we have some exciting new developments from our members worldwide! RISC-V is truly a global…
RISC-V International Newsletter – December 2023Message from RISC-V International As we look back on 2023, we wanted to express our gratitude to the entire RISC-V ecosystem. Throughout the year, we…
RISC-V International Marks Banner Year for RISC-V Adoption, Technical Momentum, and Community EngagementRISC-V adoption continues to expand across key vertical markets including aerospace, AI/ML, automotive, data center, embedded, HPC, and security Santa Clara, Calif. – Nov. 7,…
RISC-V International Newsletter – November 2023Message from RISC-V International Greetings! We’re in the final countdown to RISC-V Summit North America, which runs Nov. 6-8 in Santa Clara, CA. The anticipation and…
RISC-V International Newsletter – September 2023Message from RISC-V International RISC-V is inevitable! During the past few months, the RISC-V ecosystem has continued to grow globally. We are witnessing incredible adoption,…
RISC-V International Newsletter – May/June 2023Message from RISC-V International The growth and reach of the RISC-V ecosystem continues to inspire me during 2023! We are seeing incredible adoption across a…
Ashling and Imagination announce Ashling’s RiscFree™ C/C++ SDK support for RISC-V-based Catapult family.Embedded World, Mar-14 2023, Nuremberg, Germany. Ashling and Imagination Technologies announced today that Ashling’s RiscFree SDK will provide software development support for Imagination’s Catapult RISC-V-based…
RISC-V Newsletter – March 2, 2023RISC-V Momentum We’re off to an incredible start in 2023! We have already ratified several extensions and are on course to complete six ratifications in…
First-ever RISC-V Summit Europe Will Demonstrate Technical and Commercial Momentum Across IndustriesThe Barcelona RISC-V Summit from June 5-9 to focus on industries such as Automotive, High Performance Compute/Data Center, and Security; Call for Submissions and Sponsorships…
RISC-V Honors Outstanding Technical and Community Contributions for 2022Recipients Selected from Tens of Thousands of Engineers Working on RISC-V Initiatives Globally San Jose, Calif. – Dec. 21, 2022 – RISC-V International, the global…
RISC-V Sees Significant Growth and Technical Progress in 2022 with Billions of RISC-V Cores in MarketRISC-V Summit brings together the global RISC-V community after a banner year San Jose, Calif. – Dec. 13, 2022 – RISC-V International, the global open…
RISC-V Global Summit Will Showcase Enormous Momentum for the Open Standard Hardware Architecture and Software Ecosystem | RISC-V InternationalCall for Proposals, Sponsorship Sales, and Attendee Registration Now Open Event Spans December 12th through 15th; Summit Sessions Are December 13th and 14th San…
RISC-V 2024: A Year of Global Growth and InnovationAs 2024 comes to a close, it’s clear that this has been a transformative year for RISC-V. From achieving industry firsts to driving innovation across…
S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPCS2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC December 19, 2024 – S2C, a global leader in FPGA-based prototyping solutions,…
My Journey with the RISC-V Mentorship | Sailing Downstream IIby Linda Njau, RISC-V Mentee at Ventana Micro SystemsI came across the Linux/RISC-V mentorship while searching for an internship, and my curiosity was sparked by…
XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative ComputingWeitong Su, Alibaba DAMO Academy Co-processors are specialized units designed to assist the main processor in executing specific tasks, such as graphics processing and signal…
Enhancing the Future of AI/ML with Attached Matrix ExtensionZhao Jiang, Alibaba DAMO Academy In recent years, the rapid advancement of AI technologies, particularly deep learning, has significantly increased the demand for computing power,…
Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career PivotAndrea Gallo, RVFA Vice President of Technology at RISC-V InternationalAfter decades of a highly successful, Arm-focused career, Andrea Gallo was ready to take his professional…
Triton kernel performance on RISC-V CPUIntroduction to Triton Triton is an open-source, Python-based Domain-Specific Language (DSL) developed by OpenAI to simplify the writing of high-performance GPGPU code. It was first…
Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMsBy Deke Wang and David Chen, Stream Computing In the wave of digital transformation, the intelligent upgrade of community services has become key to improving…
Stream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix ImplementationBy Fujie Fan and David Chen, Stream Computing Background: In order to solve the problem of instruction fragmentation of RISC-V in AI field and accelerate…
Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoTDOME Cybersecurity provides a flexible Software Development Kit (SDK) for connecting the PolarFire FPGA to the IoT By: Harry Ostaffe Vice President, Marketing @ Veridify…
RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source InnovationsOn October 17, the inaugural RISC-V Eco-system Development Forum, held as part of the Guangdong-Hong Kong-Macao Greater Bay Area Semiconductor Industry Expo, took place at…
Chile’s First Steps with RISC-V: Paving the Way for Technological InnovationChile is embarking on an exciting journey into the world of RISC-V. As the country takes its initial steps with RISC-V, there is growing enthusiasm…
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RISC-V 2024: A Year of Global Growth and InnovationAs 2024 comes to a close, it’s clear that this has been a transformative year for RISC-V. From achieving industry firsts to driving innovation across…
S2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPCS2C Launches Prodigy S8-100 Series: 100M Gate FPGA Prototyping for AI and HPC December 19, 2024 – S2C, a global leader in FPGA-based prototyping solutions,…
My Journey with the RISC-V Mentorship | Sailing Downstream IIby Linda Njau, RISC-V Mentee at Ventana Micro SystemsI came across the Linux/RISC-V mentorship while searching for an internship, and my curiosity was sparked by…
XuanTie Co-Processor Interface Solution: A Bridge to Efficient Collaborative ComputingWeitong Su, Alibaba DAMO Academy Co-processors are specialized units designed to assist the main processor in executing specific tasks, such as graphics processing and signal…
Enhancing the Future of AI/ML with Attached Matrix ExtensionZhao Jiang, Alibaba DAMO Academy In recent years, the rapid advancement of AI technologies, particularly deep learning, has significantly increased the demand for computing power,…
Meet Andrea Gallo, RVFA: A Senior IT Leader’s Career PivotAndrea Gallo, RVFA Vice President of Technology at RISC-V InternationalAfter decades of a highly successful, Arm-focused career, Andrea Gallo was ready to take his professional…
Triton kernel performance on RISC-V CPUIntroduction to Triton Triton is an open-source, Python-based Domain-Specific Language (DSL) developed by OpenAI to simplify the writing of high-performance GPGPU code. It was first…
Stream Computing Provides Smart Community Services Based on RISC-V Computing Power and LLMsBy Deke Wang and David Chen, Stream Computing In the wave of digital transformation, the intelligent upgrade of community services has become key to improving…
Stream Computing RISC-V Matrix Extension Open Source Project Upgrades to Version 0.5, Supporting Vector+Matrix ImplementationBy Fujie Fan and David Chen, Stream Computing Background: In order to solve the problem of instruction fragmentation of RISC-V in AI field and accelerate…
Real-Time, Zero-Trust Cybersecurity for the PolarFire® SoC and IoTDOME Cybersecurity provides a flexible Software Development Kit (SDK) for connecting the PolarFire FPGA to the IoT By: Harry Ostaffe Vice President, Marketing @ Veridify…
RISC-V Forum Shenzhen: Unleashing Power of Electronics Making to Lead Global Open-Source InnovationsOn October 17, the inaugural RISC-V Eco-system Development Forum, held as part of the Guangdong-Hong Kong-Macao Greater Bay Area Semiconductor Industry Expo, took place at…
Chile’s First Steps with RISC-V: Paving the Way for Technological InnovationChile is embarking on an exciting journey into the world of RISC-V. As the country takes its initial steps with RISC-V, there is growing enthusiasm…
Leveraging Formal Verification to find critical RTL bugs in a RISC-V core – a LUBIS EDA best practiceIn an industry where missed corner cases can delay products by weeks or even months, LUBIS EDA recently demonstrated how formal verification can catch critical…
RISC-V basics: The truth about custom extensionsThe era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI),…
EE Times: China Unyielding Ascent in RISC-VAs a participant at the recent RISC-V Summit in Shanghai, I witnessed firsthand the sheer scale and unwavering resolve with which China is strategically investing…
Ashling Announces RiscFree™ Debug and Trace Support for Tenstorrent TT-Ascalon™ RISC-V CPUsSilicon Valley, CA – August 6th, 2025 – Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK.…
S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit ChinaShanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at…
Legendary GPU architect Raja Koduri’s new startup leverages RISC-V and targets CUDA workloads — Oxmiq Labs supports running Python-based CUDA applications unmodified on non-Nvidia hardwareRaja Koduri, a legendary GPU architect from ATI Technologies, AMD, Apple, and Intel, on Tuesday said he had founded a new GPU startup that emerged…
Enabling Space-Grade AI/ML with RISC-V: A Fully European Stack for Autonomous MissionsAs modern space missions evolve in complexity, the role of software onboard spacecraft is undergoing a dramatic transformation. Spacecraft are no longer limited to basic telemetry and…
RISC-V’s Ascent Could Reshape The Global Compute LandscapeFor decades, chip architectures have been dominated by a pair of towering incumbents—x86 and Arm—defining and powering everything from laptops to hyperscale data centers. But…
How Next-Gen Chips Are Unlocking RISC-V’s Customization AdvantageAs semiconductor applications continue to diversify, the traditional one-size-fits-all processor model is becoming increasingly outdated. Today’s designs demand greater specialization to meet the unique performance,…
Nvidia to bring CUDA platform support to the RISC-VNvidia announced it is working to bring CUDA platform support to the RISC-V instruction set architecture (ISA) at the 2025 RISC-V Summit in China, with…
Three high-performance RISC-V processors to watch in H2 2025: UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3Some high-performance RISC-V processors are in the pipeline for the rest of the year 2025, namely UltraRISC UR-DP1000, Zhihe A210, and SpacemIT K3. We currently…
Breakthrough in Automotive AI: Running BEVFormer on SiFive’s Early Access RISC-V Intelligence XM PlatformPavel Chupin, Senior Director of AI Software, SiFive We’re excited to share the successful deployment of the BEVFormer model on SiFive’s Intelligence XM IP, an…