No recent posts listed
RISC-V: The AI-Native Platform for the Next Trillion Dollars of Compute
Quintauris and TASKING join forces to power RISC-V in automotive
Microchip’s PolarFire® SoC FPGA Meets Beagle Board: High-Performance SoC with BeagleV®-Fire
Design Approaches and Architectures of RISC-V SoCs
Leveraging Formal Verification to find critical RTL bugs in a RISC-V core – a LUBIS EDA best practice
From Simulation Bottlenecks to Formal Confidence: Leveraging Formal for Exhaustive RISC-V Verification
RISC-V basics: The truth about custom extensions
Arteris’ Multi-Die Solution for the RISC-V Ecosystem
CVA6 RISC-V PMP Vulnerabilities against FIA
EE Times: China Unyielding Ascent in RISC-V
Ashling Announces RiscFree™ Debug and Trace Support for Tenstorrent TT-Ascalon™ RISC-V CPUs
S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit China
RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V International
Intel Corporation Makes Deep Investment in RISC-V Community to Accelerate Innovation in Open Computing
RISC-V Celebrates Incredible Year of Growth and Progress, Ratifying Multiple Technical Specifications, Launching New Education Programs, and Accelerating Broad Industry Adoption
Ventana Micro Systems Inc. Joins RISC-V International’s Board of Directors
RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V Designs
RISC-V Launches the Open Hardware Diversity Alliance
The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San Francisco
RISC-V International and seL4 Foundation Announce New Security Milestone
RISC-V International Welcomes Chengwei Capital as a Premier Member
CHIPS Alliance and RISC-V International Invite the RISC-V Community to Participate in Updating a New Unified Memory Architecture Standard
Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V InternationalRISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension
RISC-V Summit North America 2024: Keynotes and Industry Tracks
Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!
Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEE
AI/ML Innovations at RISC-V Summit North America: A Track to Watch
Join Us for the RISC-V Hackathon at Summit North America 2024!
RISC-V Processor Design – Free YouTube Course by Maven Silicon
Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze ToolsDebugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® Tools
Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged Upstream
TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector ProcessorRivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoC
Leveraging a Passion for Logic into a RISC-V Career
RISC-V Summit North America 2024: Keynotes and Industry TracksDon’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEEAI/ML Innovations at RISC-V Summit North America: A Track to WatchJoin Us for the RISC-V Hackathon at Summit North America 2024!RISC-V Processor Design – Free YouTube Course by Maven SiliconGet Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze ToolsDebugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® ToolsBox64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged UpstreamTetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector ProcessorRivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoCLeveraging a Passion for Logic into a RISC-V Career
Nvidia’s CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm
RISC-V Solidifies Presence in China as Global Momentum Builds
ESWIN Computing Partners with Canonical to Put Ubuntu on Its New EBC77 Series RISC-V SBCs
The installed base of RT-Thread operating system has exceeded 2.5 billion units and is actively developing RISC-V industry layout
GlobalFoundries to Acquire MIPS to Accelerate AI and Compute Capabilities
Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor Computing
Quintauris and WHS Will Work on RISC-V for Automotive
Telink Semiconductor Launches ML7218 & ML3219 Modules: A New Choice for Smart IoT with Low-Power Innovation
Nuclei System Technology Releases UX1030H with Full Support for RVA23
Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo
Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed Boost
Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V Power
RISC-V: The AI-Native Platform for the Next Trillion Dollars of ComputeWe explore how companies across industries are proving the viability of RISC-V as a native architecture for modern AI workloads
Quintauris and TASKING join forces to power RISC-V in automotiveQuintauris and TASKING have announced a new partnership to strengthen RISC-V development for the automotive industry. As part of this collaboration, Quintauris will integrate TASKING’s RISC-V compiler…
Microchip’s PolarFire® SoC FPGA Meets Beagle Board: High-Performance SoC with BeagleV®-FireThe BeagleV®-Fire board from BeagleBoard.org features Microchip’s PolarFire® SoCs, harnessing its RISC-V and FPGA technology, creating a powerful platform for innovation. As part of Microchip’s Mi-V ecosystem, it benefits from a rich set…
Design Approaches and Architectures of RISC-V SoCsAuthor: P R Sivakumar, Founder and CEO, Maven Silicon We design different kinds of System-on-Chips (SoCs/Chips) tailored for different electronic products. Let’s explore how we…
Leveraging Formal Verification to find critical RTL bugs in a RISC-V core – a LUBIS EDA best practiceIn an industry where missed corner cases can delay products by weeks or even months, LUBIS EDA recently demonstrated how formal verification can catch critical…
From Simulation Bottlenecks to Formal Confidence: Leveraging Formal for Exhaustive RISC-V VerificationIntroduction Various methods are used for design verification, including simulation, emulation, and formal verification. While simulation and emulation are effective at identifying bugs, they may…
RISC-V basics: The truth about custom extensionsThe era of universal processor architectures is giving way to workload-specific designs optimized for performance, power, and scalability. As data-centric applications in artificial intelligence (AI),…
Arteris’ Multi-Die Solution for the RISC-V Ecosystemby Ashley Stevens, Director of Product Management and Marketing at Arteris The amount of compute used to train frontier AI models has been doubling roughly…
CVA6 RISC-V PMP Vulnerabilities against FIAProject Snapshot Fault Injection Attacks (FIA) present considerable threats to the security and reliability of embedded systems. FIAs can compromise an embedded processor by altering…
EE Times: China Unyielding Ascent in RISC-VAs a participant at the recent RISC-V Summit in Shanghai, I witnessed firsthand the sheer scale and unwavering resolve with which China is strategically investing…
Ashling Announces RiscFree™ Debug and Trace Support for Tenstorrent TT-Ascalon™ RISC-V CPUsSilicon Valley, CA – August 6th, 2025 – Ashling today announced full debug and trace support for Tenstorrent’s Ascalon RISC-V CPU within its RiscFree SDK.…
S2C Advances RISC-V Ecosystem, Accelerating Innovation at 2025 Summit ChinaShanghai, July 19, 2025 — S2C, a leader in functional verification, showcased its latest digital EDA solutions and key partnerships with BOSC, Xuantie, and Andes Technology at…
RISC-V Announces First New Specifications of 2022, Adding to 16 Ratified in 2021 | RISC-V InternationalEfficient Trace, Supervisor Binary Interface, Unified Extensible Firmware Interface, and Zmmul Multiply-Only Extension Accelerate Embedded- and Large-System Design. Six Additional Specifications Already In the Pipeline…
RISC-V welcomes Intel to the Board of Directors to collaborate on RISC-V IP and contribute engineering expertise to accelerate RISC-V software development ZURICH – February…
RISC-V Celebrates Incredible Year of Growth and Progress, Ratifying Multiple Technical Specifications, Launching New Education Programs, and Accelerating Broad Industry AdoptionWith billions of chips in the market, RISC-V has seen widespread commercial adoption across industries and implementations, from embedded automotive to hyperscale AI, from 5G…
Ventana Micro Systems Inc. Joins RISC-V International’s Board of DirectorsVentana will continue to contribute and accelerate technical progress and market adoption of RISC-V ZURICH – Dec. 6, 2021 – RISC-V International, a global open hardware…
RISC-V International Ratifies 15 New Specifications, Opening Up New Possibilities for RISC-V DesignsNew Vector, Scalar Cryptography and Hypervisor specifications will help accelerate the adoption of RISC-V across a variety of market segments. ZURICH – Dec. 2,…
RISC-V Launches the Open Hardware Diversity AllianceFounded in Collaboration with the CHIPS Alliance, OpenPOWER Foundation, and Western Digital, the Alliance is Focused on Providing Support Programs, Learning Opportunities, and Mentoring for…
The 2021 RISC-V Summit Will Demonstrate Adoptions and Technical Advances This December in San FranciscoZURICH and SAN FRANCISCO – July 28, 2021 – RISC-V International announced the 2021 RISC-V Summit that will bring together the open hardware community for…
RISC-V International and seL4 Foundation Announce New Security MilestoneSAN FRANCISCO, May 5, 2021 – Today, the seL4 Foundation and RISC-V International announced that the verified seL4 microkernel on the RV64 architecture has been…
RISC-V International Welcomes Chengwei Capital as a Premier MemberInvestment firm Chengwei Capital to join the RISC-V Board of Directors and Technical Steering Committee Zurich – April 29, 2021 – RISC-V International, a non-profit…
CHIPS Alliance and RISC-V International Invite the RISC-V Community to Participate in Updating a New Unified Memory Architecture StandardNew joint working group will enhance the OmniXtend Cache Coherency architecture SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its…
Learn About the RISC-V ISA with Two Free Training Courses from The Linux Foundation and RISC-V InternationalThe online courses are offered on edX.org and will make RISC-V training more accessible SAN FRANCISCO - EMBEDDED WORLD - March 2, 2021 – The…
RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause ExtensionRISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension Fast Track significantly accelerates the ratification of small architecture extensions Zurich – Feb.…
RISC-V Summit North America 2024: Keynotes and Industry TracksThe RISC-V Summit North America 2024 is a pivotal event for the RISC-V community, bringing together innovators, developers, and thought leaders who are driving advancements…
Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!The RISC-V Summit North America 2024 is fast approaching, and it's a must-attend event for those interested in shaping the future RISC-V and open standards.…
Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEEBy Erhu Feng (Shanghai Jiao Tong University), Qingyu Shang (Shanghai Jiao Tong University), Yu-Chien Lin (Andes), Che-Chia Chang (Andes), Bing Gui (Nuclei) Introduction There has…
AI/ML Innovations at RISC-V Summit North America: A Track to WatchRegistration prices for RISC-V Summit North America 2024 increase after Oct 11. Register today to sit in on AI/ML presentations and more. Artificial Intelligence (AI)…
Join Us for the RISC-V Hackathon at Summit North America 2024!We’re excited to team up with our members Andes, Codasip, and Tactical Computing Laboratories to bring you an in-person hackathon at this year’s RISC-V Summit…
RISC-V Processor Design – Free YouTube Course by Maven SiliconIn this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how chip designers design various chips,…
Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze ToolsBy: Matej Antonijevic (TASKING) Developers who have struggled with achieving real-time performance and security in embedded systems can now look forward to unprecedented capabilities thanks…
Debugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® ToolsBy: Frank Riemenschneider, Senior Marketing Engineer at Lauterbach GmbH Microchip's PolarFire® System-on-Chip Field-Programmable Gate Array (SoC FPGA) family implements a total of five SiFive U54…
Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged UpstreamThe Box64 RISC-V backend has implemented scalar instructions to emulate x86_64 vector extensions like MMX and SSE*, ensuring good compatibility with the rv64gc architecture. However,…
TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector ProcessorBy Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications…
Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoCNX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024—…
Leveraging a Passion for Logic into a RISC-V CareerThe path to success for an IT career is often paved with curiosity, dedication and a willingness to evolve. Victor Labián Carro, RVFA, now a…
No recent posts listed
RISC-V Summit North America 2024: Keynotes and Industry TracksThe RISC-V Summit North America 2024 is a pivotal event for the RISC-V community, bringing together innovators, developers, and thought leaders who are driving advancements…
Don’t Miss Out: RISC-V Summit North America 2024 – Register Before Prices Increase!The RISC-V Summit North America 2024 is fast approaching, and it's a must-attend event for those interested in shaping the future RISC-V and open standards.…
Towards Generic RISC-V TEE Ecosystem with Penglai and OP-TEEBy Erhu Feng (Shanghai Jiao Tong University), Qingyu Shang (Shanghai Jiao Tong University), Yu-Chien Lin (Andes), Che-Chia Chang (Andes), Bing Gui (Nuclei) Introduction There has…
AI/ML Innovations at RISC-V Summit North America: A Track to WatchRegistration prices for RISC-V Summit North America 2024 increase after Oct 11. Register today to sit in on AI/ML presentations and more. Artificial Intelligence (AI)…
Join Us for the RISC-V Hackathon at Summit North America 2024!We’re excited to team up with our members Andes, Codasip, and Tactical Computing Laboratories to bring you an in-person hackathon at this year’s RISC-V Summit…
RISC-V Processor Design – Free YouTube Course by Maven SiliconIn this course, our Founder and CEO, Mr. P R Sivakumar, explains the layered architecture of RISC-V open ISA and how chip designers design various chips,…
Get Started With Real-Time Systems Using Microchip’s PolarFire® SoC FPGA and TASKING Debug and Analyze ToolsBy: Matej Antonijevic (TASKING) Developers who have struggled with achieving real-time performance and security in embedded systems can now look forward to unprecedented capabilities thanks…
Debugging of PolarFire® SoC FPGAs Made Easy with Lauterbach’s TRACE32® ToolsBy: Frank Riemenschneider, Senior Marketing Engineer at Lauterbach GmbH Microchip's PolarFire® System-on-Chip Field-Programmable Gate Array (SoC FPGA) family implements a total of five SiFive U54…
Box64 Adds Initial Support for RISC-V Vector 1.0 (RVV) Extension, Achieves up to 300% Performance Boost, Code Now Open-Source and Merged UpstreamThe Box64 RISC-V backend has implemented scalar instructions to emulate x86_64 vector extensions like MMX and SSE*, ensuring good compatibility with the rv64gc architecture. However,…
TetraMem Integrates Energy-Efficient In-Memory Computing with Andes RISC-V Vector ProcessorBy Wenbo Yin, Vice President of IC Design, TetraMem Inc. Introduction The rapid proliferation of artificial intelligence (AI) across a growing number of hardware applications…
Rivos Selects Andes NX45 for Control Functions in Upcoming High-Performance RISC-V SoCNX45 Becomes the Only RISC-V Core to Pass Rivos’ Rigorous Verification Process After Extensive Evaluation of Leading RISC-V Cores San Jose, CA – Sep. 11, 2024—…
Leveraging a Passion for Logic into a RISC-V CareerThe path to success for an IT career is often paved with curiosity, dedication and a willingness to evolve. Victor Labián Carro, RVFA, now a…
Nvidia’s CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and ArmAt the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform will be made compatible with the RISC-V instruction set architecture (ISA)…
RISC-V Solidifies Presence in China as Global Momentum BuildsThe open standard RISC-V instruction set architecture is rapidly expanding its global footprint, with China emerging as a significant force in its development and adoption.…
ESWIN Computing Partners with Canonical to Put Ubuntu on Its New EBC77 Series RISC-V SBCsESWIN Computing has announced its own Raspberry Pi-inspired single-board computer (SBC) family, the EBC77 Series, built around its four-core EIC7700X RISC-V system-on-chip — and it's…
The installed base of RT-Thread operating system has exceeded 2.5 billion units and is actively developing RISC-V industry layoutXinhua Finance, Shanghai, June 24 (Reporter Gao Shaohua) Shanghai Ruiside Electronic Technology Co., Ltd. recently brought its core product RT-Thread open source operating system to…
GlobalFoundries to Acquire MIPS to Accelerate AI and Compute CapabilitiesMALTA, N.Y. and SAN JOSE, Calif., July 08, 2025 (GLOBE NEWSWIRE) -- GlobalFoundries (Nasdaq: GFS) (GF) today announced a definitive agreement to acquire MIPS, a…
Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor ComputingSan Jose, CA – July 7, 2025 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member…
Quintauris and WHS Will Work on RISC-V for AutomotiveQuintauris, the company founded as a single source to enable compatible RISC-V-based products, is pleased to announce a new strategic partnership with WITTENSTEIN high integrity…
Telink Semiconductor Launches ML7218 & ML3219 Modules: A New Choice for Smart IoT with Low-Power InnovationIn the surging tide of the IoT, wireless communication modules serve as the crucial connection points between devices and networks, driving the widespread adoption of…
Nuclei System Technology Releases UX1030H with Full Support for RVA23Shanghai, June 24, 2025 — As the RISC-V ecosystem continues to evolve toward greater standardization and high-performance computing, the demand for processors that offer virtualization, secure…
Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea GalloDan is joined by Andrea Gallo, CEO of RISC-V International, the non-profit home of the RISC-V instruction set architecture standard, related specifications, and stakeholder community. Prior…
Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed BoostMicrochip has announced the latest entry in the Mi-V ecosystem: Mi-V RV32 v4.0, a soft-core RISC-V processor for use with the company's field-programmable gate array…
Introducing Mi-V RV32 v4.0 Soft Processor: Enhanced RISC-V PowerImagine a rocket, meticulously engineered for efficiency, speed and reliability, ready to launch into the vast expanse of space. The Mi-V RV32 v4.0 soft RISC-V…