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Breakthrough in Automotive AI: Running BEVFormer on SiFive’s Early Access RISC-V Intelligence XM Platform
Nvidia’s CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and Arm
RISC-V Solidifies Presence in China as Global Momentum Builds
ESWIN Computing Partners with Canonical to Put Ubuntu on Its New EBC77 Series RISC-V SBCs
The installed base of RT-Thread operating system has exceeded 2.5 billion units and is actively developing RISC-V industry layout
GlobalFoundries to Acquire MIPS to Accelerate AI and Compute Capabilities
Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor Computing
Quintauris and WHS Will Work on RISC-V for Automotive
Telink Semiconductor Launches ML7218 & ML3219 Modules: A New Choice for Smart IoT with Low-Power Innovation
Nuclei System Technology Releases UX1030H with Full Support for RVA23
Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea Gallo
Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed Boost
Happy 10th Birthday RISC-V!RISC-V International and GlobalPlatform Partner to Enhance Security Design of IoT DevicesRISC-V Foundation Announces Ratification of the Processor Trace Specification
Exploring the RISC-V Summit 2024: Technical Sessions Announced
Trailblazers: Board of Directors Technical Award Winners 2024SpacemiT Key Stone K1 AI CPU has been adapted to the FedoraMore than 1,300 Attendees Expected at RISC-V Summit China Next Week
Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applications
Open source System on Module with Microchip PolarFire SoCDefining RISC-V CPUs in Renode simulation with custom instructions and extensions
Debugging of RISC-V-Based Chips Made Easy
New Launch: Advanced RISC-V Courses | Maven Silicon
How ChipFlow is Making the Impossible Possible
RT-Thread: Pioneering Real-Time Operating System for RISC-VMETASAT Project Celebrates 18 Months of Innovation: Key Developments in Satellite Technology
Exploring the RISC-V Summit 2024: Technical Sessions AnnouncedTrailblazers: Board of Directors Technical Award Winners 2024SpacemiT Key Stone K1 AI CPU has been adapted to the FedoraMore than 1,300 Attendees Expected at RISC-V Summit China Next WeekMicrochip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applicationsOpen source System on Module with Microchip PolarFire SoCDefining RISC-V CPUs in Renode simulation with custom instructions and extensionsDebugging of RISC-V-Based Chips Made EasyNew Launch: Advanced RISC-V Courses | Maven SiliconHow ChipFlow is Making the Impossible PossibleRT-Thread: Pioneering Real-Time Operating System for RISC-VMETASAT Project Celebrates 18 Months of Innovation: Key Developments in Satellite Technology
AMD’s Kernel Compute Driver “AMDKFD” Can Now Be Enabled On RISC-VInnatera’s Neuromorphic Pulsar Microcontroller Takes Center Stage at COMPUTEX 2025
5 RISC-V SBCs That Are Worth Using
Aion Silicon wins $12M deal for RISC-V HPC, AI design work
RISC-V Turns 15 With Fast Global Adoption
15 Years of Lauterbach & RISC-V: Enabling Great Chips, Superb IP and Future-proven Applications
The RISC-V World Sees Changes, Milestones, and Innovations
Boosting RISC-V SoC performance for AI and ML applications
Andrea Gallo Takes Over as RISC-V International’s New CEO
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-V
RISC-V Technology Seeing Growing Maturity and Penetration
Automotive Industry Charts New Course with RISC-V
Breakthrough in Automotive AI: Running BEVFormer on SiFive’s Early Access RISC-V Intelligence XM PlatformPavel Chupin, Senior Director of AI Software, SiFive We’re excited to share the successful deployment of the BEVFormer model on SiFive’s Intelligence XM IP, an…
Nvidia’s CUDA platform now supports RISC-V — support brings open source instruction set to AI platforms, joining x86 and ArmAt the 2025 RISC-V Summit in China, Nvidia announced that its CUDA software platform will be made compatible with the RISC-V instruction set architecture (ISA)…
RISC-V Solidifies Presence in China as Global Momentum BuildsThe open standard RISC-V instruction set architecture is rapidly expanding its global footprint, with China emerging as a significant force in its development and adoption.…
ESWIN Computing Partners with Canonical to Put Ubuntu on Its New EBC77 Series RISC-V SBCsESWIN Computing has announced its own Raspberry Pi-inspired single-board computer (SBC) family, the EBC77 Series, built around its four-core EIC7700X RISC-V system-on-chip — and it's…
The installed base of RT-Thread operating system has exceeded 2.5 billion units and is actively developing RISC-V industry layoutXinhua Finance, Shanghai, June 24 (Reporter Gao Shaohua) Shanghai Ruiside Electronic Technology Co., Ltd. recently brought its core product RT-Thread open source operating system to…
GlobalFoundries to Acquire MIPS to Accelerate AI and Compute CapabilitiesMALTA, N.Y. and SAN JOSE, Calif., July 08, 2025 (GLOBE NEWSWIRE) -- GlobalFoundries (Nasdaq: GFS) (GF) today announced a definitive agreement to acquire MIPS, a…
Andes Technology Advances High-Performance RISC-V Strategy with U.S.-based Design Center: Condor ComputingSan Jose, CA – July 7, 2025 – Andes Technology (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099), the leading supplier of high-efficiency, low-power 32/64-bit RISC-V processor cores and founding premier member…
Quintauris and WHS Will Work on RISC-V for AutomotiveQuintauris, the company founded as a single source to enable compatible RISC-V-based products, is pleased to announce a new strategic partnership with WITTENSTEIN high integrity…
Telink Semiconductor Launches ML7218 & ML3219 Modules: A New Choice for Smart IoT with Low-Power InnovationIn the surging tide of the IoT, wireless communication modules serve as the crucial connection points between devices and networks, driving the widespread adoption of…
Nuclei System Technology Releases UX1030H with Full Support for RVA23Shanghai, June 24, 2025 — As the RISC-V ecosystem continues to evolve toward greater standardization and high-performance computing, the demand for processors that offer virtualization, secure…
Podcast EP294: An Overview of the Momentum and Breadth of the RISC-V Movement with Andrea GalloDan is joined by Andrea Gallo, CEO of RISC-V International, the non-profit home of the RISC-V instruction set architecture standard, related specifications, and stakeholder community. Prior…
Microchip Upgrades Its Mi-V RV32 RISC-V Soft-Core Processor, Promises a Major Speed BoostMicrochip has announced the latest entry in the Mi-V ecosystem: Mi-V RV32 v4.0, a soft-core RISC-V processor for use with the company's field-programmable gate array…
Happy 10th Birthday RISC-V!It is hard to believe, but the RISC-V project is ten years old today! RISC-V at HotChips, Flint Center, Cupertino CA, August 2014 After careful…
RISC-V International and GlobalPlatform Partner to Enhance Security Design of IoT DevicesIndustry associations collaborate to drive open source standards that simplify security design for hardware developers and enhance the security of IoT devices and processors May…
RISC-V Foundation Announces Ratification of the Processor Trace SpecificationRatification signifies another breakthrough for the thriving RISC-V ecosystem San Francisco – March 9 2020 – The RISC-V Foundation, a non-profit corporation controlled by its…
Exploring the RISC-V Summit 2024: Technical Sessions AnnouncedThe RISC-V Summit North America Plenary Sessions are now live on the event website. Each year, we are continually impressed with the high caliber of…
Trailblazers: Board of Directors Technical Award Winners 2024By: Iris Zheng, Digital Marketing Intern, RISC-V International Five technical leaders were honored at RISC-V Summit Europe 2024 for their remarkable contributions to the RISC-V…
SpacemiT Key Stone K1 AI CPU has been adapted to the FedoraSpacemiT Key Stone K1 AI CPU has been adapted to the Fedora operating system successfully. With the Fedora operating system successfully running on the MUSE…
More than 1,300 Attendees Expected at RISC-V Summit China Next WeekCheck out all the impressive talks and co-located events Next week, from August 21-23, more than 1,300 attendees will gather at the Huanglong Hotel in…
Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applicationsBy: Barry Kavanagh, Chief Executive Officer, O.C.E. Technology Ltd. Polarfire® SoC FPGA RISC-V space applications can now take advantage of an RTOS compliant to ESA…
Open source System on Module with Microchip PolarFire SoCThe PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks…
Defining RISC-V CPUs in Renode simulation with custom instructions and extensionsBy: Antmicro The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger…
Debugging of RISC-V-Based Chips Made EasyFROM SIMPLE MICROCONTROLLERS TO COMPLEX MULTICORE SOCS RISC-V cores can be found in increasingly more chips, either as the main CPU(s) or as a companion…
New Launch: Advanced RISC-V Courses | Maven SiliconBy: Maven Silicon We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and…
How ChipFlow is Making the Impossible PossibleWith Innovative technology, a collaborative spirit and a unique value proposition, Chip flow is setting itself to be the next generation of semiconductor solutions. Interview…
RT-Thread: Pioneering Real-Time Operating System for RISC-VIn the realm of modern computing architectures, the emergence of RISC-V marks a significant development, offering unprecedented openness and flexibility for processor design and implementation.…
METASAT Project Celebrates 18 Months of Innovation: Key Developments in Satellite TechnologyJuly 1st, 2024 – The METASAT Project, a European Commission-funded initiative aimed at transforming satellite technology is pleased to announce significant progress after a year…
No recent posts listed
Exploring the RISC-V Summit 2024: Technical Sessions AnnouncedThe RISC-V Summit North America Plenary Sessions are now live on the event website. Each year, we are continually impressed with the high caliber of…
Trailblazers: Board of Directors Technical Award Winners 2024By: Iris Zheng, Digital Marketing Intern, RISC-V International Five technical leaders were honored at RISC-V Summit Europe 2024 for their remarkable contributions to the RISC-V…
SpacemiT Key Stone K1 AI CPU has been adapted to the FedoraSpacemiT Key Stone K1 AI CPU has been adapted to the Fedora operating system successfully. With the Fedora operating system successfully running on the MUSE…
More than 1,300 Attendees Expected at RISC-V Summit China Next WeekCheck out all the impressive talks and co-located events Next week, from August 21-23, more than 1,300 attendees will gather at the Huanglong Hotel in…
Microchip, and O.C.E. Technology deliver high-reliability RTOS for Polarfire® SoC FPGA space applicationsBy: Barry Kavanagh, Chief Executive Officer, O.C.E. Technology Ltd. Polarfire® SoC FPGA RISC-V space applications can now take advantage of an RTOS compliant to ESA…
Open source System on Module with Microchip PolarFire SoCThe PolarFire SoC was the world’s first Linux-enabled mass market multi-core RISC-V SoC, originally made available pre-silicon by Microchip through Antmicro’s Renode simulation framework. Thanks…
Defining RISC-V CPUs in Renode simulation with custom instructions and extensionsBy: Antmicro The openness and customizability of the RISC-V ISA has encouraged its use across a variety of scenarios, such as supporting cores in larger…
Debugging of RISC-V-Based Chips Made EasyFROM SIMPLE MICROCONTROLLERS TO COMPLEX MULTICORE SOCS RISC-V cores can be found in increasingly more chips, either as the main CPU(s) or as a companion…
New Launch: Advanced RISC-V Courses | Maven SiliconBy: Maven Silicon We are delighted to inform you that we have recently published Advanced RISC-V Processor IP Design and Verification Online Courses. Our Founder and…
How ChipFlow is Making the Impossible PossibleWith Innovative technology, a collaborative spirit and a unique value proposition, Chip flow is setting itself to be the next generation of semiconductor solutions. Interview…
RT-Thread: Pioneering Real-Time Operating System for RISC-VIn the realm of modern computing architectures, the emergence of RISC-V marks a significant development, offering unprecedented openness and flexibility for processor design and implementation.…
METASAT Project Celebrates 18 Months of Innovation: Key Developments in Satellite TechnologyJuly 1st, 2024 – The METASAT Project, a European Commission-funded initiative aimed at transforming satellite technology is pleased to announce significant progress after a year…
AMD’s Kernel Compute Driver “AMDKFD” Can Now Be Enabled On RISC-VFollowing all of the Linux kernel graphics driver features merged last week for the Linux 6.16 kernel, sent out this morning were the initial batch of fixes to the…
Innatera’s Neuromorphic Pulsar Microcontroller Takes Center Stage at COMPUTEX 2025In a company press release, Innatera announced its Pulsar neuromorphic microcontroller earned Best-in-Show in the Microcontrollers, Microprocessors & IP category at COMPUTEX 2025 by Embedded Computing Design.…
5 RISC-V SBCs That Are Worth UsingIf you're exploring alternatives to the Raspberry Pi, RISC-V single-board computers (SBCs) have become increasingly compelling. These open-source hardware platforms offer flexibility and performance that can rival traditional…
Aion Silicon wins $12M deal for RISC-V HPC, AI design workEnd-to-end ASIC partnership to accelerate global supercomputing market with open-standard, energy-efficient silicon. Aion Silicon announced it has secured a $12 million engagement to provide comprehensive design services for…
RISC-V Turns 15 With Fast Global AdoptionIn 2010, a modest summer project at UC Berkeley sought a suitable instruction set architecture (ISA). Now, 15 years later, RISC-V is a global alternative…
15 Years of Lauterbach & RISC-V: Enabling Great Chips, Superb IP and Future-proven ApplicationsLauterbach is not only the global market leader in development tools for embedded systems; it has been part of the RISC-V community from the very…
The RISC-V World Sees Changes, Milestones, and InnovationsIt’s been a year of change so far for the RISC-V movement, from new leadership to an outpouring of hardware. In fifteen years, RISC-V has…
Boosting RISC-V SoC performance for AI and ML applicationsToday’s system-on-chip (SoC) designs integrate unprecedented numbers of diverse IP cores, from general-purpose CPUs to specialized hardware accelerators, including neural processing units (NPUs), tensor processors,…
Andrea Gallo Takes Over as RISC-V International’s New CEORISC-V International has announced Andrea Gallo as the organization’s new CEO, effective immediately. Gallo has served as Vice President of Technology at RISC-V International since…
SiFive Collaborates with Red Hat to Support Red Hat Enterprise Linux for RISC-VDeveloper preview of Red Hat Enterprise Linux 10 on SiFive HiFive Premier P550 platform provides developers with a platform to optimize a new class of…
RISC-V Technology Seeing Growing Maturity and PenetrationAt last month’s Andes Technology RISC-V Con event in San Jose, CA, the company announced a number of partnerships with companies like Imagination Technologies, Baya…
Automotive Industry Charts New Course with RISC-VThe European automotive industry, historically characterized by long development cycles and a complex, somewhat insulated ecosystem, is fundamentally transforming, and RISC-V is rising as a…