Inaugural RISC-V Summit Proceedings
Dec. 3-6, 2018
The first annual RISC-V Summit was held Dec. 3-6, 2018 at the Santa Clara Convention Center. There were more than 1,100 registrants from 20 countries around the globe. The Summit’s Exhibit Hall featured 29 exhibitors, with an impressive 53 presentations across the two days, as well as a hackathon. We also announced the winners of the SoftCPU Contest.
Keynote sessions on Tuesday, Dec. 4 included Krste Asanović, chief architect of SiFive and professor at UC Berkeley, Martin Fink, executive vice president and chief technology officer at Western Digital, Patrick Johnson, vice president of mixed signal and FPGA business units at Microchip, and Robert Shearer, director of Silicon architecture and modeling at Facebook.
Keynote sessions on Wednesday, Dec. 5 included David Patterson, vice chair of the RISC-V Foundation, Yunsup Lee, chief technical officer of SiFive, Rob Oshana, co-chair of the program committee and vice president of software engineering at NXP, Michael Gielda, vice president of business development at Antmicro and Greg Wright, senior director of engineering at Qualcomm.
A special thanks to all of our sponsors: Lead Sponsor, Western Digital; Ruby Sponsor SiFive; Emerald Sponsor Microsemi, a subsidiary of Microchip Technology; Diamond Sponsors Antmicro, NXP and Qualcomm; and Silver Sponsors Codasip, UltraSoC and Rambus. Additionally, thanks to Ashling for sponsoring the happy hours on the first and second days of the event, and to Western Digital and SiFive for sponsoring the Innovation Celebration.
Please see the video below for highlights of the RISC-V Summit 2018:
Proceedings
Check out the slides and videos from each of the sessions below. Please find the YouTube playlist here and the Tecent videos here.Monday, Dec. 3, 2018: RISC-V Summit Pre-Conference
| Time | Event | Speaker, Affiliation | |
| 10:30am | Tutorial: Running the Zephyr RTOS and Machine Learning with TensorFlow Lite on RISC-V | Peter Warden, Google and Peter Zierhoffer, Antmicro | Slides |
| 12:00pm | Lunch | Andrew Waterman, SiFive | |
| 1:30pm | Formal Verification of RISC-V processor implementations | Edmund Humbenberger and Clifford Wolf, Symbiotic EDA | Slides |
| 1:30pm | Running a Linux-Capable Open Source Soft SoC on the Avalanche Board with MicroSemi PolarFire FPGA | Karol Gugala, Antmicro and Bill Pratt, Future Electronics | Slides |
| 3:30pm | Tutorial: Easy-to-use, FPGA-Accelerated Hardware Simulation of RISC-V Hardware Designs with FireSim on Amazon EC2 F1 | Alon Amid, Sagar Karandikar and David Biancolin, UC Berkeley | Slides |
Tuesday, Dec. 4, 2018: RISC-V Summit Day 1
| Time | Event | Speaker, Affiliation | |
| 8:20am | Welcome & RISC-V ISA & Foundation Overview | Rick O’Connor, RISC-V Foundation | Slides | Video |
| 8:40am | Keynote: RISC-V State of the Union | Krste Asanovic, SiFive | Slides | Video |
| 9:10am | Keynote: Unleashing Innovation From Core to Edge | Martin Fink, Western Digital | Slides | Video |
| 9:40am | Keynote: Enabling the Freedom to Innovate | Patrick Johnson, Microchip | Slides | Video |
| 11:00am | Keynote: The 100X Problem – How to Redefine Silicon for Augmented Reality | Robert Shearer, Facebook | |
| 12:00pm | Birds of Feather Discussion: Debugging + Tracing | Graham Markall, Embecosm | Slides |
| 1:10pm | CPU Project in Western Digital: From Embedded Cores for Flash Controllers to Vision of Datacenter Processors with Open Interfaces | Zvonimir Bandic, Dejan Vucinic and Robert Golla, Western Digital | Slides | Video |
| 1:10pm | Deterministic L2 Cache Solution and Performance in an AMP capable SoC | Cyril Jean, Microsemi | Slides | Video |
| 1:10pm | Embedded Intelligence Everywhere | Jack Kang, SiFive | Slides | Video |
| 1:35pm | Sophon Edge AI platform with RISC-V Processor | Ian Chen, Bitmain | Video |
| 1:35pm | NVIDIA’s Deep Learning Accelerator meets SiFive’s Freedom Platform | Yunsup Lee, SiFive and Frans Sijstermans, NVIDIA | Slides | Video |
| 1:35pm | Formal Methods Need Not Be Black Magic | Joseph Kiniry and Daniel Zimmerman, Galois | Slides | Video |
| 2:00pm | Analyzing the Disruptive Impact of Democratized Access to Silicon Technology | Andreas Olofsson, DARPA | Slides | Video |
| 2:00pm | SiFive Freedom Revolution: Customizable RISC-V AI Platform with HBM2 and 56-112Gb/s SerDes | Krste Asanovic, SiFive | Slides | Video |
| 2:00pm | A FIPS140-2 Compliant Trust Module for Quad 64-bit RISC-V Core Complex | Shumpei Kawasaki, SH Consulting KK and Cong-Kha Pham, University of Electro-Communications | Slides | Video |
| 2:25pm | UVM-based RISC-V Processor Verification Platform | Tao Liu and Richard Ho, Google | Slides | Video |
| 2:25pm | Hwacha: A Data-Parallel RISC-V Extension and Implementation | Colin Schmidt and Albert Ou, UC Berkeley | Slides | Video |
| 2:25pm | Architecture Design Space Exploration Using RISC-V | Donato Kava and Sahan Bandara, Boston University | Slides | Video |
| 2:50pm | Using the RISC-V PMP with an Embedded RTOS to Achieve Process Separation and Isolation | Jean Labrosse, Micrium / Silicon Labs | Slides | Video |
| 2:50pm | Embracing a System-Level Approach in the Real World: Combining Arm & RISC-V in a Heterogeneous Designs | Gajinder Panesar, UltraSoC | Slides | Video |
| 2:50pm | Making RISC-V The Most Secure Platform | Cesare Galarti, Hex Five Security | Slides | Video |
| 3:40pm | A Processor Description Language Optimized for RISC-V | Zdenek Prikryl, Codasip | Slides | Video |
| 3:40pm | Massively Parallel RISC-V Processing with Transactional Memory | Steve Zagorianakos, Netronome | Slides | Video |
| 3:40pm | Panel: RISC-V Security Ecosystem: Open for Business | Brandon Lewis, OpenSystems Media; Chaunhua Chang, Andes Technology; Cesare Galarti, Hex Five Security; Jothy Rosenberg, Dover Microsystems; and Martin Scott, Rambus | Slides | Video |
| 4:05pm | Making a Complex, Linux-enabled SoC Available to Everyone Today with Renode | Michael Gielda, Antmicro | Slides |Video |
| 4:05pm | Accelerating Computational Storage Over NVMe with RISC-V | Stephen Bates, Eideticom | Slides | Video |
| 4:30pm | AI at the Edge Using PULP + eFPGA | Timothy Saxe, QuickLogic and Luca Benini, ETH Zurich | Slides | Video |
| 4:30pm | RISC-V MultiCore Secure Boot | Pierre Selwan and Ken Irving, Microsemi, a Microchip company | Slides | Video |
| 4:55pm | Extending the RISC-V ISA for Optimized Support of CNNs in a Multi-Core Context | Eric Flamand, GreenWaves Technologies | Slides | Video |
| 4:55pm | Functional Safety and Security, ISO26262, and Their Implications for the RISC-V Ecosystem | Gajinder Panesar, UltraSoC and Francesco Rossi, ResilTech | Slides | Video |
Wednesday, Dec. 5, 2018: RISC-V Summit Day 2
| Time | Event | Speaker, Affiliation | |
| 8:30am | Keynote: A New Golden Age for Computer Architecture: History, Challenges and Opportunities | David Patterson, RISC-V Foundation | Slides | Video |
| 9:00am | Keynote: Opportunities and Challenges of Building Silicon in the Cloud | Yunsup Lee, SiFive | Video |
| 9:20am | Keynote: Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption | Rob Oshana, NXP | Slides | Video |
| 9:40am | Keynote: Accelerating Innovation: Why Google’s TPU Was Just the Start | Michael Gielda, Antmicro | Slides |Video |
| 10:40am | Keynote Panel: Opportunities and Challenges in Security for Open Source Hardware | Ed Sperling, Semiconductor Engineering; Helena Handschuh, Rambus; Joseph Kiniry, Galois and Richard Newell, Microsemi | Slides | Video |
| 11:20am | Keynote: RISC-V: Opportunities and challenges in SoCs | Greg Wright, Qualcomm Technologies | Slides | Video |
| 1:10pm | Running Other Architecture Operating Systems and Applications on RISC-V Using QEMU | Alistair Francis, Western Digital | Slides | Video |
| 1:10pm | Domain-Specific Acceleration via AndeStar V5 Processors | Charlie Su, Andes Technology Corporation | Slides | Video |
| 1:10pm | If We Get RISC-V Security Right, It Will Become the Dominate Processor in the $470B IoT Market | Jothy Rosenberg, Dover Microsystems | Slides | Video |
| 1:40pm | How to Address RISC-V Compliance in the Era of OPEN ISA and Custom Instructions | Lee Moore and Simon Davidmann, Imperas | Slides | Video |
| 1:40pm | The Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor | Polychronis Xekalakis and Christopher Celio, Esperanto Technologies | Video |
| 1:40pm | Never Again: Spectre-Proofing Chip Designs with End-to-End Formal Methods | Adam Chlipala, MIT | Slides | Video |
| 2:10pm | Accelerating Inferencing on the Edge with RISC-V | Russell Klein, Mentor, a Siemens Company | Slides | Video |
| 2:10pm | Methodologies Behind the World’s First RISC-V-based SSD Controller | Jihyo Lee, FADU | Video |
| 2:10pm | How to Protect RISC-V Against Side-Channel Attacks? | Elke De Mulder and Michael Hutter, Rambus | Slides | Video |
| 2:40pm | Command-Driven Data Transfer Protocols in RISC-V SoCs | Gavin Stark, Netronome | Slides | Video |
| 2:40pm | Machine-Readable Specifications of RISC-V ISA | Alexander Kamkin and Andrei Tatarnikov, ISP RAS | Slides | Video |
| 2:40pm | SiFive TERP: A Trusted Execution Reference Platform for Embedded Secure Applications | Palmer Dabbelt and Nathaniel Graff, SiFive | Slides | Video |
| 3:30pm | Introducing New 64GC IP in the SCRx Family of the RISC-V Compatible Cores by Syntacore | Alexander Redkin, Syntacore | Slides | Video |
| 3:30pm | RISC-V Vector Performance Analysis | Guy Lemieux, VectorBlox Computing Inc. | Slides | Video |
| 3:30pm | Keystone: An Open-Source Secure Enclave for RISC-V Processors | Dayeol Lee, UC Berkeley | Slides | Video |
| 3:55pm | Ara: 64-bit RISC-V Vector Implementation in 22nm FDSOI | Fabian Schuiki and Matheus Cavalcante, ETH Zurich | Slides | Video |
| 3:55pm | Design and Implementation of a RISC-V ISA-based In-order Dual Issue Superscalar Processor | Libin TT and S. Krishnakumar Rao, C-DAC | Slides | Video |
| 3:55pm | Establishing a Security Verification Framework For The RISC-V Architecture | Jason Oberg, Tortuga Logic | Slides | Video |
| 4:30pm | Secure Bootstrapping of Trusted Software in RISC-V | Ilia Lebedev, MIT | Slides | Video |