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Imagination reveals new power-efficient DXTP GPU for laptops and mobile devices
Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC Verification
High-schooler creates LinuxPDF: Running Linux on a RISC-V emulator inside a PDF file
The RISC-V Architecture: 16 Boards and MCUs You Should Know
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025
Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applications
RISC-V at Embedded World 2025: Innovation, Networking & Must-See Sessions
Fedora Rolling Out More RISC-V Infrastructure & Ready-To-Boot Images
AheadComputing Secures $21.5M to Drive RISC-V Innovation for AI and Cloud
Checking Out The RISC V HiFive P550 from SiFive!
Why RISC-V is a viable option for safety-critical applications
TestRIG – Randomized Testing of RISC-V CPUs
RISC-V: An Open Standard Instruction Set Architecture
RISC-V Announces Agenda for 2023 RISC-V Summit Europe
RISC-V and the Future of Machine Learning Computing
Co-developing RISC-V AI solutions using Vector Extensions in Renode with Kenning
T-Head Prototypes Innovative Hardware Support for Virtual IOMMU
[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023
How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti Picus
Chip War Without Soldiers
[WEBINAR] Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA Optimization
Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computerWearable Payment Solution Based On T-Head Security TechnologiesCommunity Growth in India through Vegathon Events | RISC-V International
RISC-V: An Open Standard Instruction Set ArchitectureRISC-V Announces Agenda for 2023 RISC-V Summit EuropeRISC-V and the Future of Machine Learning ComputingCo-developing RISC-V AI solutions using Vector Extensions in Renode with KenningT-Head Prototypes Innovative Hardware Support for Virtual IOMMU[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti PicusChip War Without Soldiers[WEBINAR] Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA OptimizationCanonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computerWearable Payment Solution Based On T-Head Security TechnologiesCommunity Growth in India through Vegathon Events | RISC-V International
Semidynamics RISC-V AI IP selected for LLM applicationsSiFive Empowers AI at Scale with RISC-V Innovation[VIDEO] RISC-V Drives the Future: From Software-Defined Vehicles to ADAS to AI (MIPS Podcast)
Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7MHow RISC-V standards are changing the world [Q&A]Interview with Calista Redmond, CEO, RISC-V InternationalRISC-V for HPC at SC24Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPC
Openchip, NEC and Barcelona Supercomputing Center studying Collaboration to develop Next Generation Supercomputers based on RISC-V
DeepComputing Launches Early Access Program for DC-ROMA RISC-V Mainboard for Framework Laptop 13
VIDEO: RISC-V Design Innovations with Custom Extensions | Synopsys
MIPS releases RISC-V CPU for autonomous vehicles
Imagination reveals new power-efficient DXTP GPU for laptops and mobile devicesImagination Technology has announced its newest GPU IP, Imagination DXTP. With 20% improved power efficiency over its predecessor DXT, Imagination brings two new RISC-V GPU models…
Breker RISC-V SystemVIP Deployed across 15 Commercial RISC-V Projects for Advanced Core and SoC VerificationSAN JOSE, Calif., Feb. 20, 2025 (GLOBE NEWSWIRE) -- Breker Verification Systems today confirmed its RISC-V SystemVIP library components and test suite synthesis product portfolio is deployed…
High-schooler creates LinuxPDF: Running Linux on a RISC-V emulator inside a PDF fileA high-schooler who goes by the online handle of ading2210 has released LinuxPDF, software that runs Linux within a PDF file. This comes after his earlier release of DoomPDF,…
The RISC-V Architecture: 16 Boards and MCUs You Should KnowMicrocontrollers are everywhere, powering everything from your dishwasher to powerful computing systems and millions of wearable and IoT devices. For the processor cores and architectures,…
RISC-V HPC excitement at Supercomputing 2024 sets up an unmissable ISC 2025By: Nick Brown, EPCC High Performance Computing (HPC) is one of the most exciting and challenging fields, solving the world's biggest problems with incredible levels…
Cortus MINERVA Out-of-Order 4GHz 64-bit RISC-V Processor Platform targets automotive applicationsDate: February 21st, 2025 Location: Mauguio - Montpellier, France Cortus, an innovative fabless semiconductor manufacturing group today announces a key achievement of its high-performance Out-of-Order…
RISC-V at Embedded World 2025: Innovation, Networking & Must-See SessionsThe RISC-V Pavilion returns to embedded world for 2025! Visit us in Hall 5, Stand 5-119, to discover the latest RISC-V technologies and applications and…
Fedora Rolling Out More RISC-V Infrastructure & Ready-To-Boot ImagesThe Fedora Project is rolling out expanded coverage of RISC-V hardware moving forward and making it easier for those with RISC-V developer boards to run…
AheadComputing Secures $21.5M to Drive RISC-V Innovation for AI and CloudPORTLAND, Ore., Feb. 19, 2025 — AheadComputing today announced it has secured $21.5 million in seed funding to rapidly develop and commercialize its advanced microprocessor architecture designed…
Checking Out The RISC V HiFive P550 from SiFive!Ever wanted to get in on the ground floor of something really cool? Wendell shows you how you can get involved with RISC V development…
Why RISC-V is a viable option for safety-critical applicationsAn intro to RISC-V As safety-critical systems become increasingly complex, the choice of processor architecture plays an important role in ensuring functional safety and system…
TestRIG – Randomized Testing of RISC-V CPUsTestRIG (Testing with Random Instruction Generation) is a testing framework for RISC-V implementations. The RISC-V community has standardized a formal model of the architecture in…
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RISC-V: An Open Standard Instruction Set ArchitectureBy Mark Himelstein, CTO of RISC-V International In this blog post, we’ll explain why RISC-V is an open standard instruction set architecture (ISA). We’ve received…
RISC-V Announces Agenda for 2023 RISC-V Summit EuropeThe first-ever RISC-V Summit Europe includes keynotes, technical talks, working groups, poster sessions, networking opportunities, and more RISC-V International will host its first annual…
RISC-V and the Future of Machine Learning ComputingBy: Charlie Cheng, Managing Director of Polyhedron LLC Andes Technology Corp. was founded in 2004 and is headquartered in Taiwan, with a significant presence in…
Co-developing RISC-V AI solutions using Vector Extensions in Renode with KenningKenning helps develop real-world Machine Learning solutions for ARM and RISC-V platforms such as NVIDIA Jetson AGX Orin, Google Coral or HiFive Unmatched by seamlessly…
T-Head Prototypes Innovative Hardware Support for Virtual IOMMUAuthor: Chong Ren Recently, T-Head has completed the QEMU-based proof-of-concept of hardware support for virtual IOMMU for virtual machines, based on the specification in the…
[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023Calista Redmond talks with John Furrier & Rob Strechay at Open Source Summit NA 2023 in Vancouver, Canada.
How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti PicusThe RISC-V Golden model, also called the Sail model, defines the instruction execution of the RISC-V architecture. As such, it is useful for evaluating the…
Chip War Without SoldiersAuthor: P R Sivakumar, Founder and CEO, Maven Silicon LinkedIn Profile: https://www.linkedin.com/in/sivapr/ Every country realizes the importance of producing skilled chip designers who could decide…
[WEBINAR] Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA OptimizationAre you developing or thinking about developing your own RISC-V processor? You’re not alone. The use of the RISC-V ISA to develop processors for SoCs…
Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computerMay 10, 2023: Canonical published the optimised Ubuntu release for StarFive’s VisionFive 2, the world’s first high-performance RISC-V single board computer (SBC) with an integrated…
Wearable Payment Solution Based On T-Head Security TechnologiesBy Xiaoxia Cui Wearable devices, such as smartwatches and pulse oximeters, are gaining popularity with the continuous expansion of IoT applications in recent years. However,…
Community Growth in India through Vegathon Events | RISC-V InternationalThirty hours! That’s how long some of the recent VEGA Processors hackathons, VEGATHON, have lasted. At a recent hackathon local RISC-V enthusiasts used the RISC-V-based…
No recent posts listed
RISC-V: An Open Standard Instruction Set ArchitectureBy Mark Himelstein, CTO of RISC-V International In this blog post, we’ll explain why RISC-V is an open standard instruction set architecture (ISA). We’ve received…
RISC-V Announces Agenda for 2023 RISC-V Summit EuropeThe first-ever RISC-V Summit Europe includes keynotes, technical talks, working groups, poster sessions, networking opportunities, and more RISC-V International will host its first annual…
RISC-V and the Future of Machine Learning ComputingBy: Charlie Cheng, Managing Director of Polyhedron LLC Andes Technology Corp. was founded in 2004 and is headquartered in Taiwan, with a significant presence in…
Co-developing RISC-V AI solutions using Vector Extensions in Renode with KenningKenning helps develop real-world Machine Learning solutions for ARM and RISC-V platforms such as NVIDIA Jetson AGX Orin, Google Coral or HiFive Unmatched by seamlessly…
T-Head Prototypes Innovative Hardware Support for Virtual IOMMUAuthor: Chong Ren Recently, T-Head has completed the QEMU-based proof-of-concept of hardware support for virtual IOMMU for virtual machines, based on the specification in the…
[INTERVIEW] Calista Redmond, RISC-V International | Open Source Summit NA 2023Calista Redmond talks with John Furrier & Rob Strechay at Open Source Summit NA 2023 in Vancouver, Canada.
How to Speed Up the Emulating Process with Pydrofoil | Carl Friedrich and Matti PicusThe RISC-V Golden model, also called the Sail model, defines the instruction execution of the RISC-V architecture. As such, it is useful for evaluating the…
Chip War Without SoldiersAuthor: P R Sivakumar, Founder and CEO, Maven Silicon LinkedIn Profile: https://www.linkedin.com/in/sivapr/ Every country realizes the importance of producing skilled chip designers who could decide…
[WEBINAR] Taking the Risk out of Developing Your Own RISC-V Processor with Fast, Architecture-Driven, PPA OptimizationAre you developing or thinking about developing your own RISC-V processor? You’re not alone. The use of the RISC-V ISA to develop processors for SoCs…
Canonical enables Ubuntu on StarFive’s VisionFive 2 RISC-V single board computerMay 10, 2023: Canonical published the optimised Ubuntu release for StarFive’s VisionFive 2, the world’s first high-performance RISC-V single board computer (SBC) with an integrated…
Wearable Payment Solution Based On T-Head Security TechnologiesBy Xiaoxia Cui Wearable devices, such as smartwatches and pulse oximeters, are gaining popularity with the continuous expansion of IoT applications in recent years. However,…
Community Growth in India through Vegathon Events | RISC-V InternationalThirty hours! That’s how long some of the recent VEGA Processors hackathons, VEGATHON, have lasted. At a recent hackathon local RISC-V enthusiasts used the RISC-V-based…
Semidynamics RISC-V AI IP selected for LLM applicationsA leading IP company for high performance, AI-enabled, RISC-V processors, Semidynamics has announced that it has been selected by UPMEM as its core provider for…
SiFive Empowers AI at Scale with RISC-V InnovationArtificial intelligence is increasingly transforming industries, and adopting RISC-V as a flexible and scalable architecture plays a significant role in this shift. Ian Ferguson, senior…
[VIDEO] RISC-V Drives the Future: From Software-Defined Vehicles to ADAS to AI (MIPS Podcast)Learn about the trends behind accelerating automotive compute in software-defined vehicles, autonomous driving, ADAS, and AI. Drew Barbier, Vice President of Product at MIPS, sits…
Ubitium Debuts First Universal RISC-V Processor to Enable AI at No Additional Cost, as It Raises $3.7MSemiconductor veterans secure $3.7M seed funding to launch a universal RISC-V processor that eliminates the need for specialized chips, enabling advanced AI at no additional…
How RISC-V standards are changing the world [Q&A]You may have heard of RISC-V -- usually pronounced 'risk-five' -- it's an instruction set architecture originally designed to support computer architecture research and education…
Interview with Calista Redmond, CEO, RISC-V InternationalCould you give us an overview of RISC-V's mission and why it's expanding so rapidly, with over 4,500 members across 70+ countries? RISC-V's rapid growth…
RISC-V for HPC at SC24RISC-V is an open Instruction Set Architecture (ISA), where the ISA can be thought of as the contract between the software and hardware worlds. Since RISC-V was…
Esperanto Technologies and NEC Cooperate on Initiative to Advance Next Generation RISC-V Chips and Software Solutions for HPCMOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Esperanto Technologies™, a leading developer of RISC-V chips and software for high-performance computing (HPC) and artificial intelligence (AI), today announced that they…
Openchip, NEC and Barcelona Supercomputing Center studying Collaboration to develop Next Generation Supercomputers based on RISC-VBarcelona / Tokyo, 14 of November 2024 –Openchip, NEC and the Barcelona Supercomputing Center are studying collaboration to develop the new Openchip Vector Computing Accelerator…
DeepComputing Launches Early Access Program for DC-ROMA RISC-V Mainboard for Framework Laptop 13DeepComputing is excited to announce the launch of an exclusive early access program for the DC-ROMA RISC-V Mainboard, specifically designed for industry and business customers.…
VIDEO: RISC-V Design Innovations with Custom Extensions | SynopsysAndes and Synopsys present a ‘software first’ design flow using virtual platforms/prototypes allows RISC-V developers to explore new hardware configuration options with application SW workloads…
MIPS releases RISC-V CPU for autonomous vehiclesMIPS released its P8700 CPU based on the RISC-V computing architecture to target driver assistance and autonomous vehicle applications. The San Jose, California-based company, which focuses…