RISC-V Summit Proceedings
December, 2019
In December, 2019, the RISC-V Foundation held its second annual RISC-V Summit in San Jose, California, US. We would like to thank all of the summit’s many sponsors and exhibitors. This page hosts the proceedings from the summit, including slides and video.Agenda and Presentation Slides
Keynotes
| Welcome Address: Exponential Progress across Industries and Around the World with RISC-V | Calista Redmond – CEO, RISC-V Foundation | Slides |  |
| State of the Union | Krste Asanovic – Professor | Chief Architect, UC Berkeley | SiFive | Slides |  |
| Unshackling Memory! | Martin Fink, Western Digital | Slides |  |
| Open for Business: True Stories of How Far We’ve Come With the RISC-V Ecosystem | Ted Speers – Head of Product Planning for FPGA Business, Microchip Technology Inc. | Slides |  |
| Lightning Talks | Marianne Damstra – CCO, Solid Sands | Slides |  |
| Stefano Giaconi – Cofounder & CTO, Chronos Tech | Slides | ||
| Ulli Mueller – Senior Vice President Sales & Marketing, Think Silicon | Slides | ||
| Ruby Sponsor SiFive presents: Taking RISC-V into New Markets | Yunsup Lee – CTO, SiFive | Slides |  |
| RISC-V and Chips Alliance Address new Compute Requirements | Zvonimir Bandic – Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance Dejan Vucinic – Director, NVM Systems Architecture, Western Digital | Slides |  |
| An Open Source Approach to System Security | Helena Handschuh – Rambus Fellow & Chair, RISC-V Foundation Security Standing Committee, Rambus | Slides |  |
| How RISC-V made the Quick Jump from Academia to Industry and Why it will Change the Entire Semiconductor Industry – a Venture Capital perspective | Stefan Dyckerhoff – Managing Director, Sutter Hill Ventures | Slides |  |
| Open Source Processor IP for High Volume Production SoCs: CORE-V Family of RISC-V Cores | Rick O’ Connor – Founder, President & CEO, OpenHW Group | Slides |  |
| Keynote Panel: Opportunity and Risks in Open Source Hardware | Krste Asanovic – Professor | Chief Architect, UC Berkeley | SiFive Mendy Furmanek – IBM Director – OpenPOWER Processor Enablement; OpenPOWER President, IBM Joseph Jacks – Founder and CEO, OSS Capital Brandon Lewis – Editor-in-Chief, Open Systems Media Tim Whitfield – VP Strategy Embedded and Automotive, ARM | Slides |  |
| Qualcomm Diamond Sponsor Session: Global Ambitions for RISC-V | Calista Redmond – CEO, RISC-V Foundation Travis Lanier – Senior Director, Product Management, Qualcomm Rob Oshana – VP Software Engineering, NXP Yu Pu – IoT SOC Lead, Alibaba | Slides |  |
| RISC-V of Samsung in the age of 5G and AI | Junho Huh – Master (Research VP), System LSI Business, Samsung Electronics | Slides |
Hardware/Architecture
| Code Size of RISC-V versus ARM using the Embench™ 0.5 Benchmark Suite: What is the Cost of ISA Simplicity? | David Patterson – Vice Chair, RISC-V Foundation | Slides |  |
| Every CPU Cycle Counts | Gajinder Panesar – CTO, UltraSoC Iain Robertson – VP Engineering, UltraSoC | Slides |  |
| A RISC-V ISA Extension for Ultra-Low Power IoT Wireless Signal Processing | Zdeněk Přikryl – CTO, Codasip | Slides |  |
| Software PPA Metrics: Results from Real-world MCU Security Applications | Joe Circello – Fellow, Chief MCU Core Platform & Security Architect, NXP Semiconductors, N.V. | Slides |  |
| An Open and Coherent Memory Centric Architecture Enabled by RISC-V | Dejan Vucinic – Director, NVM Systems Architecture, Western Digital | Slides |  |
| Ruby Sponsor SiFive presents: The Open Secure Platform Architecture of SiFive Shield | Dany Nativel – Security Director, SiFive | Slides |  |
| Software Flow for Complex SoC-FPGA | Cyril Jean – Director, Embedded Systems Solutions, Microchip Technology | Slides |  |
| Avoiding Amdahl’s Law: RISC-V Architecture Exploration for AI & ML Many-core Compute Arrays | Simon Davidmann – CEO, Imperas | Slides |  |
| Scalable, Configurable Neural Network Accelerator Based on RISC-V Core | Karthik Wali – Staff Digital Design Engineer, LG Electronics | Slides |  |
| Enabling the Full Power of a Multiprocessor SoC | Jeff Hancock – Senior Product Manager, Mentor (a Siemens Company) | Slides |  |
| RISC-V in Practical Education of Computer Architecture | Stefan Wallentowitz – Professor, Munich University of Applied Sciences | Slides |  |
| The Next Generation of GAP8: An IoT Application Processor for Inference at the Very Edge | Martin Croome – VP, Business Development, Greenwaves Technologies | Slides |  |
| Enabling AI on Low Power Endpoint Devices Utilizing the QuickLogic and SiFive Freedom Aware Templates | Brian Faith – CEO, QuickLogic Corporation | Slides |  |
| RISC-V For Heterogeneous Computing | Justin Cormack – Security Lead, Docker | Slides |  |
| Ruby Sponsor SiFive presents: The SiFive Vector Processor | Mark Throndson – Senior Director of Product Management and Marketing, SiFive | Slides |  |
| SweRV Cores Roadmap | Zvonimir Bandic – Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance Robert Golla – Senior Fellow, Western Digital | Slides |  |
| Processor IP Showcase | Kevin Chen – Senior Architect, Andes Technology | Slides |  |
| Drew Barbier – Sr. Manager, SiFive Core IP Product Marketing, SiFive | Slides | ||
| Zvonimir Bandic – Sr. Director, Next Gen Platform Technologies | Chairman of the Board, CHIPS Alliance, Western Digital | CHIPS Alliance | Coming Soon | ||
| Karel Masarik – CEO and Founder, Codasip | Slides | ||
| Arjun Menon – Senior Project Officer, IIT Madras | Shakti Project | Slides | ||
| Alexander Redkin – Executive Director, Co-Founder, Syntacore | Slides | ||
| Rick O’ Connor – Founder, President & CEO, OpenHW Group | Slides | ||
| Gajinder Panesar – CTO, UltraSoC | Coming Soon | ||
| Anand Joshi – Anlayst, Computer Vision & AI, Tractica | Slides | ||
| Innovation in CPU Architecture, Pushing Data from Edge to Cloud | Caffrey Chen – Chief Processor Architect, Alibaba | Slides |  |
| Andes RISC-V Processor Solutions: From MCU to Datacenters | Charlie Su – CTO and SVP of R&D, Andes Technology Corporation | Slides |  |
| Ara 2.0: 64-bit RISC-V Vector Processor in 22nm FD-SOI | Matheus Cavalcante – PhD Student, ETH Zurich | Slides |  |
| Prototyping RISC-V Based Heterogeneous Systems-on-Chip with the ESP Open-Source Platform | Luca Carloni – Professor, Columbia University | Slides |  |
| SafeRV: Building Blocks for Safety Critical RISC-V Systems | Neel Gala – CTO, InCore Semiconductors Pvt. Ltd. Bertrand Tavernier – VP Software Research & Technologies, Thales | Coming Soon |  |
| RISC-V Verification for Processor Cores and Optional Custom Extensions | Simon Davidmann – CEO, Imperas Lee Moore – Lead Engineer, Imperas Richard Ho – Principal Hardware Engineer, Google Doug Letcher – President and CEO, Metrics Technologies, Inc. | Coming Soon |  |
| Designing and Building Modern Modular SoCs using Open-Source Federation Tools | Jack Koenig – Engineer, SiFive | Coming Soon |  |
| GNU CGEN for RISC-V Tool Chain Customization | Mary Bennett – Engineer, University of Surrey Ed Jones – Engineer, Embecosm | Coming Soon |  |
| RISC-V Bit-Manipulation ISA Extension: Spec, Hardware, Software | Ken Dockser – Senior Director of Technology, Corporate R&D, Qualcomm Clifford Wolf – CTO, Symbiotic EDA | Coming Soon |  |
| Chipyard and FireSim: End-to-End Architecture Exploration with RISC-V SoC Generators, FPGA-Accelerated Simulation and Agile Test Chips | Alon Amid – Graduate Student, UC Berkeley David Biancolin – Ph.D Candidate, University of California, Berkeley, U.C. Berkeley Abraham Gonzalez – Ph.D. Student, U.C. Berkeley Sagar Karandikar – PhD Student, UC Berkeley, UC Berkeley Colin Schmidt – Graduate Student, UC Berkeley Jerry Zhao – PhD Student, UC Berkeley, UC Berkeley | Coming Soon |  |
Security/Verification
| Emerald Sponsor Microchip presents: Getting started with PolarFire SoC | Hugh Breslin – Design Engineer, Microchip Technology Anton Krug – Development Engineer, Microchip Technology | Slides |  |
| Architectural Extensions for a RISC-V Processor for Embedded Security | Tariq Kurd – CPU Architect, Huawei UK | Slides |  |
| System-Level Security Verification of RISC-V Based SoCs | Nicole Fern – Senior Hardware Security Engineer, Tortuga Logic, Inc. | Slides |  |
| The RISC-V Open ISA’s shock Wave of Processor Innovation that’s Causing a Seismic Shift in SoC Verification Requirements | Ann Mutschler – Executive Editor/EDA, Semiconductor Engineering Simon Davidmann – CEO, Imperas Richard Ho – Principal Hardware Engineer, Google Emerson Hsiao – Senior VP, Andes Technology USA Corp. Dave Kelf – Chief Marketing Officer, Breker Verification Systems Frank Schirrmeister – Senior Group Director, Product Management, System Development, System & Verification Group (SVG), Cadence Design Systems, Inc. Mike Thompson – Director of Verification Engineering, OpenHW Group | Slides |  |
| Introducing Scalable New Core IP for Mission Critical Use | Aniket Saha – Director of Product Marketing, SiFive Murali Vijayaraghavan – Principal Engineer, SiFive | Slides |  |
| Open Source Verification Platform for RISC-V Processors | Tao Liu – Senior Hardware Engineer, Google Richard Ho – Principal Hardware Engineer, Google | Slides |  |
| Democratising Formal Verification of RISC-V Processors | Ashish Darbari – CEO, Axiomise Limited | Slides |  |
| RISC-V and a Meta-framework Security Certification Approach for a Secure Connected World | John Boggie – Director, Head of Cybersecurity Certification, NXP Semiconductors | Slides |  |
| Formal Methods for Hardware-Software Integration on RISC-V Embedded Systems | Samuel Gruetter – PhD student in Computer Science, MIT | Slides |  |
| RISC-V Enclaves: A Clean Slate Approach To Linux Security | Cesare Garlati – Co-Founder, Hex Five Security | Slides |  |
| seL4 on RISC-V: Verified OS for True Security | Gernot Heiser – Professor UNSW Sydney and seL4 Evangelist, Data61, Data61 and UNSW Sydney | Coming Soon |  |
| RISC-V: A New Zero-Trust Model for Cyber Resilient Avionics | Kevin Kinsella – System Architect, Northrop Grumman | Slides |  |
| Different Trace Methods and Efficient Ways to Utilize Them | Thomas Andersson – Product Manager, IAR Systems Robert Chyla – Lead Emulation Architect, IAR Systems | Slides |  |
| OneSpin presents: More than the Core: Verifying RISC-V SoCs | Nicolae Tusinschi – Product Specialist Design Verification, OneSpin Solutions | Coming Soon |  |
| Debugging on Homogeneous and Heterogeneous Multicore SoCs Containing a Mix of RISC-V and non-RISC-V Cores | Hugh O’Keeffe – Engineering Director, Ashling Roisin O’Keeffe – VP, Business Enterprise, Ashling | Slides |  |
| RISC-V Processor Verification based on Open-source Framework and State-of-the-art Cloud-based Methodologies | Lee Moore – Lead Engineer, Imperas Richard Ho – Principal Hardware Engineer, Google | Coming Soon |  |
| Ruby Sponsor SiFive presents: Enabling Security with AWS Qualified IoT Devices | David Lee – Director of Product Management, SiFive | Coming Soon |  |
| Verifying RISC-V Vector and Bit Manipulation Extensions using STING Design Verification Tool | Shubhodeep Choudhury – CEO, Valtrix | Slides | Coming Soon |
| Rambus presents: Challenges and Benefits of Certification for Security Hardware | Ben Levine – Senior Director, Product Management, Rambus | Coming Soon |  |
| An Efficient Runtime Validation Framework based on the Theory of Refinement | Mitesh Jain – Staff R&D Engineer, Synopsys Inc | Slides |  |
| A Tour of the RISC-V ISA Formal Specification | Rishiyur Nikhil – CTO, Bluespec, Inc. | Coming Soon |  |
| seL4 on RISC-V Renode | Jesse Millwood – Embedded Engineer, DornerWorks | Slides |  |
| How to Secure a RISC-V System in 90 minutes – From Single Core MCU to Mixed Criticality SMP Linux | Cesare Garlati – Co-Founder, Hex Five Security Sandro Pinto – Research Scientist and Invited Professor, Universidade do Minho | Coming Soon |  |
Software
| Linux on RISC-V — Fedora and Firmware Status Update | Wei Fu – Software Engineer, Red Hat | Slides |  |
| Headline Sponsor Western Digital presents: GCC Compiler: Code Size Density | Nidal Faour – Staff Engineer, R&D Engineering – Firmware & Toolchain, CTO Group, Western Digital Ofer Shinaar – Manager, R&D Engineering – Firmware & Toolchain, CTO Group, Western Digital | Slides |  |
| Open Source Compiler Tool Chains for RISC-V: Past, Present and Future | Jeremy Bennett – Chief Executive, Embecosm | Slides |  |
| The RISC-V Journey Through Containers to the Cloud | Carlos Eduardo de Paula – Senior Cloud Architect, Red Hat | Slides |  |
| Developing with FreeRTOS and RISC-V | Richard Barry – Founder | Principal Engineer, FreeRTOS | Amazon Web Services | Coming Soon |  |
| Next-generation IDE for your RISC-V Product in 20 Minutes | Ivan Kravets – CEO, PlatformIO | Slides |  |
| SEGGER presents: Visualizing and Recording the true Runtime Behavior of a RISC-V based Application — in real-time | Axel Wolf – Sr. Staff Field Applications Engineer, SEGGER Microcontroller LLC | Slides |  |
| Code Density Improvements Beyond The C Standard Extension | Zdeněk Přikryl – CTO, Codasip | Slides |  |
| RISC-V Software State of the Union | Randy Allen – VP, RISC-V Software, SiFive | Coming Soon |  |
| Production-ready RISC-V Support in LLVM/Clang 9.0 – How we Got There and What’s Next | Alex Bradbury – Director, lowRISC CIC | Coming Soon |  |
| Integrate RISC-V to build Open Common Automotive Platform | Tiejun Chen – Technical Leader and Staff Engineer, VMware | Coming Soon |  |
| Headline Sponsor Western Digital presents: RISC-V Hypervisor Support | Alistair Francis – Principal System Engineer, Western Digital Anup Patel – Technologist, Western Digital | Coming Soon |  |
| Working Towards a Common C Library for Small RISC-V Systems | Keith Packard – Principal Engineer, SiFive | Coming Soon |  |
| Fomu: Python, RISC-V, and FPGA in your USB Port | Tim Ansell – Software Engineer, Google Michael Gielda – VP Business Development, Antmicro | Coming Soon |  |
| An Introduction to RISC-V Boot Flow | Atish Patra – Principal R&D Engineer, Western Digital Anup Patel – Technologist, Western Digital | Slides |  |