RISC-V Workshop in Barcelona
7-10 May, 2018
The RISC-V Foundation invites you to attend the RISC-V Workshop in Barcelona, Spain on 7-10 May, 2018. Co-hosted by the Barcelona Supercomputing Center (BSC) and Universitat Politècnica de Catalunya (UPC), and co-sponsored by NXP and Western Digital, the RISC-V Workshop in Barcelona will gather the RISC-V ecosystem to share notable RISC-V updates, projects and implementations.
Keynote sessions will include Robert Oshana, vice president of software engineering research and development at NXP, Martin Fink, executive vice president and chief technology officer at Western Digital, and Mateo Valero, director at the Barcelona Supercomputing Center. The three-day event schedule is as follows:
- Monday, May 7, 2018 – A half-day of tutorials from the working groups of the RISC-V technical committee. The sessions will cover topics such as base ISA ratification, BitManip, compliance, debug, formal spec, memory model, opcode space management, privilege spec, security, software toolchain and vector extensions.
- Tuesday and Wednesday, May 8-9, 2018 – Two full days of presentations on RISC-V architecture, commercial and open-source implementations, software and silicon, vectors and security, applications and accelerators, simulation infrastructure and more.
- Thursday, May 10, 2018 – The event will conclude with RISC-V Foundation meetings, restricted to members of the RISC-V Foundation. The day will consist of Technical and Marketing Committee face-to-face meetings to progress the work currently underway within our various Task Groups.
The RISC-V Foundation will also host a networking reception with poster sessions and demonstrations on Tuesday, May 8. The reception will feature the latest RISC-V implementations and innovations on the market. In addition, attendees can join one of several tours of the Barcelona Supercomputing Center during the networking reception.
Check out the full agenda for the RISC-V Workshop in Barcelona here.