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We send occasional news about RISC-V technical progress, news, and events.
Chief Architect, SiFive
Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-V ISA project at UC Berkeley, serves as chairman of RISC-V International, and cofounded SiFive Inc. to support commercial use of RISC-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.
Distinguished Engineer, Google
David Patterson is likely best-known for the book Computer Architecture: A Quantitative Approach, written with John Hennessy and for the UC Berkeley research projects Reduced Instruction Set Computers (RISC), Redundant Arrays of Inexpensive Disks (RAID), and Network of Workstations (NOW). He also served as UC Berkeley’s Computer Science Division chair, the Computing Research Association chair, and president of the Association for Computing Machinery. Additionally, David was elected to the National Academy of Engineering, the National Academy of Sciences, and shared the 2017 ACM A.M. Turing Award with Hennessy.
Senior Director of Next Generation Platform Technologies, Western Digital Corporation
Zvonimir Z. Bandić is a research staff member and senior director of Next Generation Platform Technologies at Western Digital Corporation in San Jose, Calif. He received his Bachelor of Science in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his Master of Science (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on both NAND and emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center storage and computing, including CPU, memory, networking and storage. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers.
Head of Product Architecture & Planning, Microchip
Ted Speers is head of product architecture and planning for Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is a Technical Fellow and co-inventor on 35 U.S. patents. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.
Vice President, Alibaba Group
Xiaoning Qi is the Vice President of Alibaba Group. Previously, he held senior management and technical positions in companies such as Intel, designing integrated circuits and systems. He sits on the board of directors at several other international organizations including CHIPS Alliance, EEMBC, etc. He has published more than fifty technical papers, a book, and has delivered over three dozen invited talks. He also holds two US patents. Xiaoning received his Ph.D. degree in Electrical Engineering from Stanford University.
Director of Research Center of Advanced Computer Systems (ACS) at ICT-CAS
Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Research Center of Advanced Computer Systems (ACS) of ICT-CAS. Prof. Bao founded China RSIC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 has been adopted by the industry including Alibaba, Huawei, Intel and the research community. He was a plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013. He won CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.
Founder & Managing Partner, Chengwei Capital
Eric Li is a venture capitalist in Shanghai. He is founder and managing partner of Chengwei Capital. He also serves on the boards of Stanford University’s Graduate School of Business and the Freeman Spogli Institute for International Studies (FSI). He is a trustee of Fudan University’s China Institute and chairman of its advisory council, a trustee of Asia Society Hong Kong, and a member of the Council of the International Institute for Strategic Studies (IISS), which organizes the annual Shangri-La Dialogue. He received his B.A. in economics from University of California, Berkeley, his MBA from the Graduate School of Business at Stanford University, and his Ph.D. in political science from Fudan University.
President & Co-founder, Andes Technology
Frankwell Lin is the President and co-founder of Andes Technology, which is a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores. Frankwell received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Before Andes Technology, he was the spokesperson and board member of Farady, a leading fabless ASIC and silicon IP provider. He also led ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR) in Faraday. Under his management, Andes Technology has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc. In 2015, President Lin received accolade award of Outstanding Technology Management Performance, Taiwan, for his contribution to the high-tech industry. In parallel to contribution in the industry, he also contributes time and effort in social service for technology evolution. He is Chairman of TEIA (Taiwan Embedded Industry Alliance) from 2010 to 2012. TEIA is a non-profit organization to promote embedded system innovation as well as embedded system value chain engineering talent training, including embedded software, hardware, IP, application, international promotion channel, etc.
Director, Computer Sciences Research Department, Barcelona Supercomputing Center
Jesús Labarta received a B.S. in Telecommunications Engineering from the Technical University of Catalunya (UPC) in 1981 and his Ph.D. in Telecommunications Engineering also from UPC in 1983. He is full professor of Computer Architecture at UPC since 1990 and was Director of CEPBA-European Center of Parallelism at Barcelona from 1996 to 2005. Since its creation in 2005, he has been the Director of the Computer Sciences Research Department within the Barcelona Supercomputing Center (BSC). During his 35-year academic career, Prof. Labarta has made significant contributions in programming models and performance analysis tools for parallel, multicore and accelerated systems, with the sole objective of helping application programmers to improve their understanding of their applications performance and to improve programming productivity in the transition towards very large-scale systems. Under his supervision, his research team has been developing performance analysis and prediction tools (Paraver and Dimemas) and pioneering research on how to increase the intelligence embedded in these performance tools.
Principal Architect, Rivos Inc
Ken has been designing processors for over 30 years in a variety of architectures including VAX, X86, MIPS, PowerPC, ARM and RISC-V. He has expertise in a variety of areas including computer architecture, microarchitecture, arithmetic, verification, benchmarking, software development and marketing. Ken has been active in several industry organizations including IEEE-754 Standard for Floating-Point Arithmetic, Heterogeneous System Architecture (HSA), and Embedded Microprocessor Benchmark Consortium (EEMBC). He holds 39 US patents in the area of microprocessor design. Ken is an active participant in many of the RISC-V task groups.
Co-Founder, Stream Computing
Mark is the co-founder of Stream Computing Inc. which is a startup company using RISC-V ISA to develop high power-efficiency and programmable DSA AI Processor. He is responsible for product definition, architecture and software engineering. Prior to Stream Computing, he worked for Wind River System since 2005 as the senior engineering director of Wind River China R&D Center. In Wind River, Mark led the development of multi commercial products including Wind River Linux, Hypervisor, Toolchain, etc.
R&D Director, Huawei Technologies Co., Ltd.
Mr. Matthew Leung’s main duties lie on the development of next generation processor technologies. His expertise and experience lies in the fields of VLSI design for advanced communication chipsets, microprocessors and artificial intelligence. Mr. Leung received his BSc and MSc degrees of Electrical Engineering in University of Michigan and Stanford University respectively. Before joining Huawei, he worked in Marvell Semiconductor, ASTRI, Sun Microsystems, Apple Computer, etc.
Engineering Director, Seagate Technology
Richard Bohn is an Engineering Director at Seagate Technology, the global leader in data storage solutions. A 16-year silicon industry veteran, Richard has led Seagate’s RISC-V efforts since 2015. Prior to his current role Richard held a number of technical leadership and design positions. He began his career at IBM in processor design. Passionate about the role of open standards and technology, Richard sits on the OpenTitan Technical Committee and Seagate’s Open Source Program Office core team. Richard received a Bachelor of Science and Master of Science in Electrical and Computer Engineering from Carnegie Mellon University.
Professor, Munich University of Applied Sciences
Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various RISC-V projects over the last six years. Stefan was involved in the debug task group and has recently become chair of the RISC-V SIG “Academia & Education”.
CEO, Guangdong StarFive Technology
Thomas Xu has a B.S. from Fudan University and M.S. from University of New Mexico, with a total of 26 years’ experience in semiconductor industry, more than 15 years’ experience in management and entrepreneurship. Senior specialist at semiconductor industry and entrepreneur. Mr. Xu spent 11 years in research and development of processors in Hewlett Packard, co-developed the processor of PA-RISC and Itanium, and was CEO of Polaris Microelectronics, CEO at Brite Semiconductor, VP of Marketing & Sales at C-sky, GM of C-Sky Shanghai company.
Vice President, UNISOC
Xiaofei Xia is the vice president of UNISOC. He is responsible for the marketing management that includes product planning, technical planning and marketing strategy. Previously, he worked for Huawei and had led in-house chipset platform planning for flagship smartphones since the first generation. In Huawei, he also pioneered the network and device chipset technical co-innovation with major Europe operators.
Co-Director, RIOS Laboratory
Dr. Zhangxi Tan is a co-director of the RISC-V International Open-source Laboratory (RIOS), leading open-source IP and software development that helps the RISC-V ecosystem world-class. Dr. Tan is an adjunct professor at Tsinghua-Berkeley Shenzhen Institute (TBSI). He received his PhD in computer science from UC Berkeley in 2013. He is specialized in computer architecture and VLSI designs. After graduating from Berkeley, he joined Pure Storage (NYSE: PSTG) as a Founding Engineer serving as a lead designer for Pure’s award winning FlashBlade product, which generates hundreds of million-dollar revenues every year and have many high-profile customers. Dr. Tan holds more than 20 US patents in flash storage systems and hardware accelerators. He also founded several startup companies in Silicon Valley and China in the chip design industry.
We send occasional news about RISC-V technical progress, news, and events.