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Senior Director of Technical Standards, Qualcomm
Lu Dai is a Senior Director of Technical Standards at Qualcomm Technologies, Inc., spearheading semiconductor standards efforts and relationships with industry organizations.
Lu was previously Senior Director of Engineering and led Qualcomm’s SOC design verification team and front-end methodologies and initiatives. He was also the Design Verification Lead responsible for multiple generations of premium tier platforms at Qualcomm, including the Snapdragon 8 series and products that power the Mars Perseverance rover and Ingenuity helicopter.
Prior to Qualcomm, Lu was the Design Verification Lead for Cisco’s Gigabit Switching Business Unit where he worked on multiple generations of Cat4k ASICs.
Lu is the current Chair of Accellera, Chairman of the RISC-V International Board of Directors and serves on the Board of Directors at Si2.
Lu holds a Master’s degree in Electrical Engineering from Cornell, and a Bachelor’s in Electrical Engineering and Computer Science from UC Berkeley.
Distinguished Engineer, RIOS Laboratory
David Patterson is likely best-known for the UC Berkeley research projects Reduced Instruction Set Computers (RISC) and Redundant Arrays of Inexpensive Disks (RAID) and for the book Computer Architecture: A Quantitative Approach, written with John Hennessy. He shared the 2017 ACM A.M. Turing Award and the 2022 NAE Charles Draper prize with his co-author. He also served as UC Berkeley’s Computer Science Division chair, the Computing Research Association chair, and president of the Association for Computing Machinery. He is currently a UC Berkeley Professor Emeritus and Distinguished Engineer at Google.
Technical Fellow, Microchip
Ted Speers is a Technical Fellow at Microchip’s FPGA BU, where he is responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. Ted is a RISC-V leader and evangelist and has served on the Board of Directors of RISC-V International since its inception in 2016. He joined Actel (now part of Microchip) in 1987 and held roles in process engineering and product engineering before assuming his current role in 2003. He is co-inventor on 35 U.S. patents. In his role, Ted has consistently defined first of it’s kind products, the most recent example being PolarFireSoC, the first RISC-V based SoC FPGA. Prior to joining Actel, he worked at LSI Logic. Ted has a Bachelor of Science in chemical engineering from Cornell.
Vice President, Alibaba Group
Xiaoning Qi is the Vice President of Alibaba Group. Previously, he held senior management and technical positions in companies such as Intel, designing integrated circuits and systems. He sits on the board of directors at several other international organizations including CHIPS Alliance, EEMBC, etc. He has published more than fifty technical papers, a book, and has delivered over three dozen invited talks. He also holds two US patents. Xiaoning received his Ph.D. degree in Electrical Engineering from Stanford University.
Executive Director & Co-Founder, Syntacore
Alexander is Executive Director and co-founder at Syntacore. Prior to establishing Syntacore in 2015, Alexander had more than 15 years of experience in semiconductor industry in senior engineering and management roles, including more than 12 years at Intel R&D, where he contributed both to the number of research projects and volume semiconductor products development. Alexander’s research interests are future SoC architectures and heterogeneous platforms with specific focus on emerging workloads analysis and acceleration.
Founder and CEO, Ventana Micro Systems
Balaji Baktha is founder and CEO of Ventana Micro Systems. He is an experienced semiconductor executive and serial technology entrepreneur and investor with a proven track record of over 30 years in Silicon Valley. Prior to Ventana, Balaji was founder and CEO of Veloce Technologies, the world’s first 64-bit ARM based high performance processor for cloud compute, networking, storage and embedded applications, which was subsequently acquired by AppliedMicro. Before Veloce, Balaji was the VP and GM of the Communications Business at Marvell Semiconductor. Before Marvell, Balaji co-founded Platys, a startup that pioneered iSCSI and was subsequently acquired by Adaptec (now Microsemi). Balaji is a Board Member of several startups, and a Limited Partner and Senior Advisor at several PE and venture funds.
President & Co-founder, Andes Technology
Frankwell Lin is the President and co-founder of Andes Technology, which is a leading supplier of high efficiency, low-power 32/64-bit RISC-V processor cores. Frankwell received BSEE degree of Electrophysics from the National Chiao-Tung University, Taiwan, and MSEE degree of Electrical and Computer Engineering from Portland State University, Oregon, USA. Before Andes Technology, he was the spokesperson and board member of Farady, a leading fabless ASIC and silicon IP provider. He also led ASIC business development as starting, then on-and-off leading ASIC implementation, chip backend service, IP business development, industry relationship development (IR) in Faraday. Under his management, Andes Technology has been recognized as one of leading suppliers of embedded CPU IP in semiconductor industry. Andes also won the reputation of leading technology company with awards such like 2012 EE Times worldwide Silicon 60 Hot Startups to Watch, 2015 the Deloitte Technology Fast 500 Asia Pacific award, etc. In 2015, President Lin received accolade award of Outstanding Technology Management Performance, Taiwan, for his contribution to the high-tech industry. In parallel to contribution in the industry, he also contributes time and effort in social service for technology evolution. He is Chairman of TEIA (Taiwan Embedded Industry Alliance) from 2010 to 2012. TEIA is a non-profit organization to promote embedded system innovation as well as embedded system value chain engineering talent training, including embedded software, hardware, IP, application, international promotion channel, etc.
Vice President of Hardware Engineering, NVIDIA
Frans Sijstermans earned his MSc degree in Computer Science from the Eindhoven University of Technology in 1985. He worked as a researcher at Philips in The Netherlands and Palo Alto, USA, until 1998. After that he held various managerial positions at Philips Semiconductors, TriMedia, and Equator. He joined NVIDIA in 2004, where he is responsible for all RISC-V processors, security IP, video codecs, camera & display controllers, vision & DL accelerators, and GSYNC products. He has been active in the open source community as a member of the inaugural board of the RISC-V foundation and the Alliance for Open Media. Also, his team open sourced NVDLA, NVIDIA’s inferencing accelerator.
Senior Director for Intel Foundry Services (IFS) at Intel Corporation
Gary Martz is a Senior Director for Intel Foundry Services (IFS) at Intel Corporation. He is leading RISC-V initiatives & solutions, collecting and driving customer requirements into RISC-V specifications and open source software projects. Gary’s Intel career spans several decades, starting as a motherboard and systems manufacturing engineer for Intel’s original server business unit. His experience at Intel also includes the Client Group, Data Center Group, Intel Labs, Wireless Communications, Reseller Channel Group, and most recently prior to joining IFS, leading standards for Intel’s Industrial Solutions Division, defining and executing the strategy for technology standards and open source software for the Industry 4.0 transformation.
Gary has served in a number of industry leadership roles, most recently serving on the board of directors for The Open Group and the steering committee for the OPC Foundation’s Field Level Communications Group. Previously Gary has represented Intel on the board of directors for the Open Connectivity Foundation, the Open Mobile Alliance, and the Wi-Fi Alliance. Gary holds a Bachelor of Science degree in Industrial Engineering from the University of Washington (’95) and an MBA from the University of Michigan’s Ross School of Business (’00).
Director of Operations, Phytium Technology
Dr. Henry He is the Director of Operations at Phytium Technology. He used to be a processor R & D engineer and worked in the field of computer architecture for more than ten years. At present, he is engaged in some management work, and responsible for the marketing management that includes product planning, technical planning and marketing strategy. He likes making friends and singing.
Director, Computer Sciences Research Department, Barcelona Supercomputing Center
Jesús Labarta received a B.S. in Telecommunications Engineering from the Technical University of Catalunya (UPC) in 1981 and his Ph.D. in Telecommunications Engineering also from UPC in 1983. He is full professor of Computer Architecture at UPC since 1990 and was Director of CEPBA-European Center of Parallelism at Barcelona from 1996 to 2005. Since its creation in 2005, he has been the Director of the Computer Sciences Research Department within the Barcelona Supercomputing Center (BSC). During his 35-year academic career, Prof. Labarta has made significant contributions in programming models and performance analysis tools for parallel, multicore and accelerated systems, with the sole objective of helping application programmers to improve their understanding of their applications performance and to improve programming productivity in the transition towards very large-scale systems. Under his supervision, his research team has been developing performance analysis and prediction tools (Paraver and Dimemas) and pioneering research on how to increase the intelligence embedded in these performance tools.
President and Founder, Codasip GmbH
Dr Karel Masařík undertook research in the use of processor architecture description languages and design automation tool at Brno University of Technology. This included research into hardware/software co-design as well as formal and functional verification of processor designs. He achieved a Ph.D. in Computer Science in 2008. He led the development of Codasip’s underlying technologies as part of the technological incubator and then founded Codasip private company in 2014. Codasip launched its processor development toolset, Codasip Studio, in 2014 and announced its first RISC-V processor core in late 2015. As Codasip’s CEO, Dr Masařík has led the company through its seed funding round in 2014 also consequent founding rounds till end 2021 and has overseen Codasip international expansion. From the end of 2021, Dr Masařík is acting as President responsible for the advanced research in the areas as security, automotive, cloud-based EDA, university programs, graphics and AI/ML.
Chief Architect, SiFive
Krste Asanović is a professor in the EECS Department at the University of California, Berkeley (UC Berkeley). He received a PhD in Computer Science from UC Berkeley in 1998 then joined the faculty at MIT, receiving tenure in 2005, before returning to join the faculty at UC Berkeley in 2007. His main research areas are computer architecture, VLSI design, parallel programming and operating system design. He is currently director of the UC Berkeley ASPIRE lab tackling the challenge of improving computational efficiency now that transistor scaling is ending. He leads the free RISC-V ISA project at UC Berkeley, serves as chairman of RISC-V International, and cofounded SiFive Inc. to support commercial use of RISC-V processors. He received the NSF CAREER award, and is an ACM Distinguished Scientist and an IEEE Fellow.
Director of Engineering, Google Android
Lars Bergstrom is a Director of Engineering at Google on the Android team, working on their platform programming languages, including Java, C/C++, and Rust and the supporting tools and libraries. He also serves as Google’s Corporate Director to the Rust Foundation. Before Google, he was at Mozilla Research, initially contributing to the Servo browser project and directing the integration of Rust into Firefox and the partner ecosystem. Later, he led Mozilla’s AR and VR work, shipping software and building OEM relationships on many different devices. He received his Ph.D. in Computer Science from the University of Chicago in 2013.
Chief Strategy Officer & Co-Founder, Rivos Inc.
Mark Hayter is Chief Strategy Officer & Co-Founder of Rivos Inc. For the previous 11 years he was Senior Engineering Director in the Chrome OS Hardware team at Google. His team developed new technologies for Chromebooks, produced reference implementations and worked with OEMs to bring them to market. Prior to that he was involved in systems architecture at several semiconductor companies, being VP of Systems Engineering at P.A. Semi, Inc. (acquired by Apple Inc.), Senior Manager of Hardware Systems Engineering at Broadcom Corporation and System Architect at SiByte, Inc. Earlier, Hayter was at the Digital Equipment Corporation Systems Research Center. Hayter holds a PhD from the University of Cambridge Computer Laboratory.
R&D Director, Huawei Technologies Co., Ltd.
Mr. Matthew Leung’s main duties lie on the development of next generation processor technologies. His expertise and experience lies in the fields of VLSI design for advanced communication chipsets, microprocessors and artificial intelligence. Mr. Leung received his BSc and MSc degrees of Electrical Engineering in University of Michigan and Stanford University respectively. Before joining Huawei, he worked in Marvell Semiconductor, ASTRI, Sun Microsystems, Apple Computer, etc.
Chief Technologist & Founder, VRULL GmbH
Dr. Philipp Tomsich is the Chief Technologist and Founder of VRULL, an engineering consultancy focused on building, enabling, and optimizing the software ecosystems for next-generation silicon solutions.
CEO and Co-Founder, Akeana
Engineering Director, Seagate Technology
Richard Bohn is an Engineering Director at Seagate Technology, the global leader in data storage solutions. A 16-year silicon industry veteran, Richard has led Seagate’s RISC-V efforts since 2015. Prior to his current role Richard held a number of technical leadership and design positions. He began his career at IBM in processor design. Passionate about the role of open standards and technology, Richard sits on the OpenTitan Technical Committee and Seagate’s Open Source Program Office core team. Richard received a Bachelor of Science and Master of Science in Electrical and Computer Engineering from Carnegie Mellon University.
Vice President of Compute, Imagination Technologies
Shreyas is currently Vice President of Compute at Imagination, responsible for Imagination’s CPU, AI and Heterogeneous compute products and solutions.
He has spent over 20 years in the technology industry both at start-ups and in large corporations in various roles. He started his journey in the UK designing CPUs at Arm before moving to a start-up, Apical, where he was a core catalyst in its successful journey from an early start up stage through to acquisition. At Apical his roles included Head of Engineering and Head of Strategic Marketing. Apical was acquired by Arm and its technology has found its way into 2billion+ devices. After spending a further few years at Arm looking after product management, he joined Imagination in 2019 to work on business development and then moved into a product leadership and strategy role.
Shreyas holds an MBA from University of Cambridge – Judge Business School, Masters in Analogue and Digital IC Design from Imperial College London, graduating top of his class with distinction. Shreyas is also the recipient of the prestigious Bhamashah award (India) and a double gold medallist for his B.Eng. in Electronics and Communications.
Professor, Munich University of Applied Sciences
Stefan is a professor at Munich University of Applied Sciences. He is a long term advocate and active member of the open source silicon community, most prominent in his role as director of the Free and Open Source Silicon Foundation (FOSSi Foundation). He has been active in various RISC-V projects over the last six years. Stefan was involved in the debug task group and has recently become chair of the RISC-V SIG “Academia & Education”.
Senior Vice President Engineering, Solutions Group at Synopsys
Dr. Yankin Tanurhan, Senior Vice President Engineering, Solutions Group at Synopsys is responsible for the Synopsys Processor IP, Security IP, Wireless Interface IP, Smart Subsystems and Non-Volatile Memory businesses. The products in his portfolio include low-power and high-performance ARC embedded CPUs, NPUs, DSPs targeting markets from Mobile, IoT, Embedded Vision, AI/ML, Digital Home, Automotive/Industrial, Security to Storage, ASIP tools with products like ASIP Designer and Programmer, IP Subsystems products like Sensor Fusion, Audio, Vision and Security Subsystems and CMOS-based Non-Volatile OTP and MTP memory IP blocks. His teams additionally develop a wide variety of Security IP from TRNGs to full blown HSMs and IDEs. Lately he extended the R&D activities into Bluetooth and Zigbee products.
Dr Tanurhan has authored 100+ papers in refereed publications. He holds a B.S. and M.S. in Electrical and Computer Engineering from Rheinisch Westfaellische Technische Hochschule (RWTH) in Aachen, Germany and a Dr. Ing. degree summa cum laude in Electrical Engineering from the University of Karlsruhe (TH) in Karlsruhe, Germany.
Chief Scientist, Beijing Institute of Open Source Chip
Yungang Bao is a Professor of Institute of Computing Technology (ICT), Chinese Academy of Sciences (CAS) and the director of Research Center of Advanced Computer Systems (ACS) of ICT-CAS. Prof. Bao founded China RISC-V Alliance (CRVA) and serves as the secretary-general of CRVA. His research interests include computer architecture and computer systems. His research work such as Labeled von Neumann Architecture (LvNA), Hybrid Memory Trace Tool (HMTT), Partition-Based DMA Cache and PARSEC 3.0 has been adopted by the industry including Alibaba, Huawei, Intel and the research community. He was a plenary keynote speaker at China National Computer Congress (CNCC) in 2016 and was invited to give a keynote presentation at ARM Research Summit 2018. He was the winner of CCF-Intel Young Faculty Award of the year for 2013. He won CCF-IEEE CS Young Computer Scientist Award and China’s National Lofty Honor for Youth under 40 of the year for 2019.
We send occasional news about RISC-V technical progress, news, and events.