The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by RISC-V International contributing members within the RISC-V International Technical Working Groups. Work on the specification is performed on GitHub, and the GitHub issue mechanism can be used to provide input into the specification.

If you would like more information on becoming a member, please see the membership page.

ISA Specification

The specifications shown below represent the current, ratified releases. Work is being done on GitHub.

  • Volume 1, Unprivileged Spec v. 20191213  [PDF]
  • Volume 2, Privileged Spec v. 20190608  [PDF]

Past ratified releases include the term “ratified” in the release tag.

Debug Specification

This is the currently ratified specification:

  • External Debug Support v. 0.13.2 [PDF] [GitHub]

This is the current stable draft:

  • External Debug Support v. 1.0.0-STABLE [PDF]

Trace Specification

The processor trace specification was approved on March 20, 2020.

Compatibility Test Framework

The RISC-V Architectural Compatibility Test Framework Version 2 is now available. This framework compares arbitrary models against a reference signature, and currently covers RV[32|64]IMC unprivileged specifications only. Tests for the not-yet-ratified Crypto Scalar extension and RV32EMC extensions are also available.

Work on Version 3.0 framework (RISCOF) is underway which will compare two arbitrary models against each other (one of which should be a reference model), expand the configurations covered, and will automatically select tests according to the model configuration.

The RISC-V ISA specification allows many architectural implementation choices. A tool has been created to describe implementation configurations (RISCV-CONFIG) that the RISCOF Framework will use to select and configure tests.

Original Specifications

Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanović, “The RISC-V Instruction Set Manual, Volume I: Base User-Level ISA”
Technical Report UCB/EECS-2011-62, EECS Department, University of California, Berkeley, May 13, 2011

Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović, “The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.0”,
Technical Report UCB/EECS-2014-54, EECS Department, University of California, Berkeley, May 7, 2014

Andrew Waterman, Yunsup Lee, Rimas Avižienis, David A. Patterson, and Krste Asanović, “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.7”
Technical Report UCB/EECS-2015-49, EECS Department, University of California, Berkeley, May 9, 2015.

Andrew Waterman, Yunsup Lee, David A. Patterson, and Krste Asanović, “The RISC-V Compressed Instruction Set Manual, Version 1.7”
Technical Report UCB/EECS-2015-157, EECS Department, University of California, Berkeley, May 28, 2015.

Andrew Waterman, Yunsup Lee, David Patterson, Krste Asanović, “The RISC-V Instruction Set Manual, Volume I: User-Level ISA Version 2.1”,
Technical Report UCB/EECS-2016-118, EECS Department, University of California, Berkeley, May 31, 2016.

Andrew Waterman, Yunsup Lee, Rimas Avižienis, David A. Patterson, and Krste Asanović, “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture Version 1.9”,
Technical Report UCB/EECS-2016-129, EECS Department, University of California, Berkeley, July 8, 2016