The RISC-V instruction set architecture (ISA) and related specifications are developed, ratified and maintained by RISC-V International contributing members within the RISC-V International Technical Working Groups. Work on the specification is performed on GitHub, and the GitHub issue mechanism can be used to provide input into the specification.

If you would like more information on becoming a member, please see the membership page.

ISA Specification

The specifications shown below represent the current, ratified releases:

  • Volume 1, Unprivileged Spec v. 20191213  [PDF] [GitHub (latest)]
  • Volume 2, Privileged Spec v. 20190608  [PDF] [GitHub (latest)]

Debug Specification

  • External Debug Support v. 0.13.2 [PDF]

Trace Specification

The processor trace specification was ratified in February, 2020.

Compliance Framework

The RISC-V Compliance Framework Version 0.1 is now available. This framework compares arbitrary models against a reference signature, and currently covers RV32IMC unprivileged spec only.

Work on Version 0.2 framework is underway which will compare two arbitrary models against each other (one of which can be a reference model), expand the configurations covered, and will automatically select tests according to the model configuration.

The RISC-V spec allows many architectural implementation choices. A repository has been created to describe implementation configurations (RISCV-CONFIG) that the Framework will use to select & configure tests.