RISC-V Workshop in Chennai

July 18-19, 2018

The RISC-V Foundation invites you to attend the RISC-V Workshop in Chennai, India on July 18-19, 2018. Hosted by The Indian Institute of Technology Madras (IIT Madras) and sponsored by Western Digital, the RISC-V Workshop in Chennai will discuss current and prospective RISC-V projects and implementations, as well as influence the future evolution of the instruction set architecture (ISA) from Silicon Valley to Silicon Fenn and beyond.
The RISC-V Workshop in Chennai will include in-depth technical presentations and updates on the RISC-V architecture, a speaking lineup from leading technology companies and research institutions in the RISC-V ecosystem, ample opportunity for networking and a demo zone to explore the latest innovations in the market. For more information, please visit the event page here.
To register for the event, please click here.

Agenda:

Wednesday, July 18, 2018

Time	Event	Speaker, Affiliation
8:00 am	Registration & Breakfast
8:55 am	Welcome address and about the Workshop	Kamakoti Veezinathan, IIT Madras and G S Madhusudan, InCore Semiconductors
9:00 am	RISC-V ISA & Foundation Overview	Rick O’Connor, RISC-V Foundation
9:15 am	RISCV ISA: Understanding Limitations and Methods to Improve Code Density & Performance	Gnanasekar Rajakumar and Ravikumar Gaddam, Western Digital
9:30 am	Going Beyond the RISC-V General Purpose Solutions	Neel Gala, InCore Semiconductors
10:00 am	Architecture Exploration of RISC-V Processor and Comparison with ARM Cortex A53 and A72	Karthikeyan Sugumaran, Mirabilis Design and Tom Jose, Mirabilis Design
10:30 am	Networking Break
11:00 am	It’s Not About the Core, It’s About the System	Gajinder Panesar, UltraSoC
11:30 am	RiTA: RISC-V Trace Analyzer	Anmol Sahoo, IIT Madras and Neel Gala, InCore Semiconductors
11:45 am	KEYNOTE: RISC-V: Enabling a New Era of Open Data-Centric Computing Architectures	Vivek Tyagi, Western Digital
12:10 pm	Networking Lunch
13:30 pm	Accelerating the RISC-V Revolution: Unleashing Custom Silicon with Revolutionary Design Platforms and Custom Accelerators	Huzefa Cutlerywala, SiFive
14:00 pm	Mi-V RISC-V Embedded Ecosystem	Krishnakumar Ranamoorthi, Microsemi
14:15 pm	Verification of the PULPino SoC platform using UVM	Mahesh R, Cisma Consultants Pvt. Ltd. and Shamanth HK, Cisma Consultants
14:30 pm	Porting Graphical Stacks to RISC-V using QEMU and Yocto	Atish Patra, Western Digital
14:45 pm	Networking Break
15:15 pm	Panel: Security & Safety Critical Systems	Vivek Tyagi, Western Digital Konala Varma, Intel Mahesha Nanjundaiah, HPE Asutosh Upadhyay, Axilor Ventures Amudhan Balasubramanian, HCL Technologies G S Madhusudan, InCore Semiconductors
16:15 pm	Poster / Demo Previews	Andrea Bocco, CEA-Leti Shubhodeep Choudhury, Valtrix Tiago Jost, ENS Paris and CEA Kevin McDermott, Imperas Software Atish Patra, Western Digital Gajinder Panesar, UltraSoC
17:00 pm	Evening Reception, Poster Sessions and Demos

Thursday, July 19, 2018

Time	Event	Speaker, Affiliation
8:00 am	Registration & Breakfast
9:00 am	RISC-V Software Development Methodology for RISC-V Devices with RTOS and Linux or Both	Kevin McDermott, Imperas Software
9:30 am	Linux Kernel on RISC-V: Where do we stand?	Atish Patra and Damien Le Moal, Western Digital
10:00 am	A Comprehensive Framework For Power-based Side-channel Leakage Evaluation of SHAKTI C-Class	Muhammad Arsath and Chester Rebeiro, IIT Madras
10:30 am	Networking Break
11:00 am	RISECREEK: From RISC-V Spec to 22FFL Silicon	Vinod Ganesan and Gopinathan Muthuswamy, IIT Madras
11:30 am	Shakti M-Class Libre RISC-V SoC	Luke Leighton, Independent
12:00 pm	SLSV : The Shakti LockStep Verification Framework	Paul George and Lavanya Jagan, IIT Madras
12:30 pm	Networking Lunch
14:00 pm	A Survey of E31 RISC-V Core Floor-Plan and Its Impact on Power, Performance and Area (PPA)	Kunal Ghosh and Anagha Ghosh, VLSI System Design
14:30 pm	Integrating Gen-Z in Server-Class RISC-V Processors	Mohan Pathasarathy, HPE
15:00	Formal Specification of the RISC-V Instruction Set Architecture	Rishiyur Nikhil and Niraj Sharma, Bluespec
15:30 pm	RISC-V Workshop Chennai Conclusion	Rick O’Connor, RISC-V Foundation

RISC-V Workshop in Chennai