Agenda For Inaugural RISC-V Summit in Santa Clara, Calif. from Dec. 3-6

Inaugural RISC-V Summit Agenda

Dec. 3-6, 2018

The RISC-V Foundation announced the agenda for its first annual RISC-V Summit at the Santa Clara Convention Center in Santa Clara, Calif. from Dec. 3-6, 2018. The Summit, in partnership with Informa’s Knowledge & Networking Division, KNect365, will gather the RISC-V ecosystem for a multi-track conference featuring keynotes, tutorials, exhibitions and networking receptions. The RISC-V Summit will host multi-track technical sessions, an exhibition hall and will feature keynotes from Antmicro, Facebook, Microchip, NXP, Qualcomm, SiFive and Western Digital.

The RISC-V Foundation workshops and events around the world celebrate the growth of the ecosystem and showcase major projects and successful technology using the RISC-V ISA. As the RISC-V ecosystem has grown rapidly over the past few years, the RISC-V Foundation’s membership now includes more than 150 organizations, individuals, academics and universities from 25 countries around the world.

This will be a three day event broken down as follows:

  • Monday, Dec. 3, 2018 – Pre-conference day reserved for on-site registration, networking, initial tutorials and the welcome party.
  • Tuesday and Wednesday, Dec. 4-5, 2018 – These two days will follow the traditional two-day format used at previous workshops with presentations covering various RISC-V projects underway within the RISC-V community and will include a poster / demo reception on Tuesday evening.
  • Thursday, Dec. 6, 2018 – The week of the Summit will conclude with RISC-V Foundation member meetings with attendance restricted to members of the RISC-V Foundation.  The day will consist of Technical and Marketing Committee face to face meetings to progress the work currently underway within our various Task Groups.

Monday, Dec. 3, 2018 RISC-V Summit Pre-Conference

Time Event Speaker, Affiliation
9:00am Registration is open from 9:00 a.m. – 6:00 p.m.
10:30am How to Get Started on RISC-V on Zephyr
12:00pm Lunch
1:30pm Formal Verification of RISC-V processor implementations Edmund Humbenberger and Clifford Wolf, Symbiotic EDA
1:30pm How to Get Started on RISC-V with Linux
3:00pm Networking Break
3:30pm Tutorial: Easy-to-use, FPGA-Accelerated Hardware Simulation of RISC-V Hardware Designs with FireSim on Amazon EC2 F1 Sagar Karandikar and David Biancolin, UC Berkeley
5:00pm Welcome Party


Tuesday, Dec. 4, 2018 RISC-V Summit Day 1


Time Event Speaker, Affiliation
8:00am Registration is open from 7:30 a.m. – 6:30 p.m.
8:30am Welcome & RISC-V ISA & Foundation Overview Rick O’Connor, RISC-V Foundation
8:50am Keynote: RISC-V State of the Union Krste Asanovic, SiFive and RISC-V Foundation
9:20am Keynote: Unleashing Innovation From Core to Edge Martin Fink, Western Digital
9:40am Keynote: Enabling the Freedom to Innovate Patrick Johnson, Microchip
10:00am Networking Break
10:00am Exhibit Hall Opens
10:40am Keynote Panel: Government Initiatives with RISC-V, Silicon Independence and Innovation
11:20am Keynote: The 100X Problem – How to Redefine Silicon for Augmented Reality Robert Shearer, Facebook
11:40am Lunch
12:00pm Birds of Feather Discussion: Debugging + Tracing Graham Markall, Embecosm
1:10pm CPU Project in Western Digital: From Embedded Cores for Flash Controllers to Vision of Datacenter Processors with Open Interfaces Zvonimir Bandic and Dejan Vucinic, Western Digital
1:10pm Formal Methods Need Not Be Black Magic Joseph Kiniry and Daniel Zimmerman, Galios
1:35pm Analyzing the Disruptive Impact of Democratized Access to Silicon Technology Andreas Olofsson, DARPA
1:35pm NVIDIA’s Deep Learning Accelerator meets SiFive’s Freedom Platform Yunsup Lee, SiFive and Frans Sijstermans, NVIDIA
1:35pm A FIPS140-2 Compliant Trust Module for Quad 64-bit RISC-V Core Complex Shumpei Kawasaki, SH Consulting KK and Kesami Hagiwara, University of Electro-Communications
2:25pm UVM-based RISC-V Processor Verification Platform Tao Liu and Richard Ho, Google
2:25pm SiFive Freedom Revolution: Customizable RISC-V AI Platform with HBM2 and 56-112Gb/s SerDes Krste Asanovic, SiFive
2:25pm Architecture Design Space Exploration Using RISC-V Donato Kava and Sahan Bandara, Boston University
2:50pm Using the RISC-V PMP with an Embedded RTOS to Achieve Process Separation and Isolation Jean Labrosse, Micrium / Silicon Labs
2:50pm Hwacha: A Data-Parallel RISC-V Extension and Implementation Colin Schmidt and Albert Ou, UC Berkeley
2:50pm RISC-V MultiCore Secure Boot Pierre Selwan and Ken Irving, Microsemi, a Microchip company
3:10pm Networking Break
3:40pm Panel Discussion: Driving innovation with Open RISC-V Platforms
3:40pm Massively Parallel RISC-V Processing with Transactional Memory Gavin Stark and Steve Zagorianakas, Netronome
3:40pm Panel: Building a More Secure World with RISC-V
4:05pm Accelerating Computational Storage Over NVMe with RISC-V Stephen Bates, Eideticom
4:30pm Explore how to Integrate RISC-V to Build Open Common Automotive Platform Teijun Chen, VMware
4:30pm AI at the Edge Using PULP + eFPGA Timothy Saxe, QuickLogic; Luca Benini, ETH Zurich
4:30pm Functional Safety and Security, ISO26262, and Their Implications for the RISC-V Ecosystem Gajinder Panesar, UltraSoC and Francesco Rossi, ResilTech
4:55pm Making a Complex, Linux-enabled SoC Available to Everyone Today with Renode Michael Gielda, Antmicro
4:55pm Extending the RISC-V ISA for Optimized Support of CNNs in a Multi-Core Context Eric Flamand, Greenwaves Technologies
5:30pm Happy Hour on the Expo Floor


Wednesday, Dec. 5, 2018 RISC-V Summit Day 2


Time Event Speaker, Affiliation
8:00am Registration is open from 8:00 a.m. – 5:30 p.m.
8:25am Welcome
8:30am Keynote: A New Golden Age for Computer Architecture: History, Challenges and Opportunities David Patterson, RISC-V Foundation
9:00am Keynote: Opportunities and Challenges of Building Silicon in the Cloud Yunsup Lee, SiFive
9:20am Keynote: Deepening the RISC-V Ecosystem to Drive Industry-Wide Adoption Rob Oshana, NXP
9:40am Keynote: Accelerating Innovation: Why Google’s TPU Was Just the Start Michael Gielda, Antmicro
10:00am Networking Break on the Expo Floor
10:00am Expo Floor Open
10:40am Keynote Panel: Secure RISC-V
11:20am Keynote: RISC-V: Opportunities and challenges in SoCs Qualcomm
11:40am Lunch
1:10pm Running Other Architecture Operating Systems and Applications on RISC-V Using QEMU Alistair Francis, Western Digital
1:10pm Domain-Specific Acceleration via AndeStar V5 Processors Charlie Su, Andes Technology Corporation
1:10pm If We Get RISC-V Security Right, It Will Become the Dominate Processor in the $470B IoT Market Jothy Rosenberg, Dover Microsystems
1:35pm How to Address RISC-V Compliance in the Era of OPEN ISA and Custom Instructions Lee Moore and Simon Davidmann, Imperas
1:35pm The Esperanto ET-Maxion High Performance Out-of-Order RISC-V Processor Polychronis Xekalakis and Christopher Celio, Esperanto Technologies
1:35pm Never Again: Spectre-Proofing Chip Designs with End-to-End Formal Methods Adam Chlipala, MIT
2:05pm Accelerating Inferencing on the Edge with RISC-V Russell Klein, Mentor, a Siemens Company
2:05pm Methodologies Behind the World’s First RISC-V-based SSD Controller Jihyo Lee, FADU
2:05pm How to Protect RISC-V Against Side-Channel Attacks? Elke De Mulder and Michael Hutter, Rambus
2:30pm Networking Break
3:00pm Command-Driven Data Transfer Protocols in RISC-V SoCs Gavin Stark, Netronome
3:00pm  RISC-V Vector Performance Analysis Guy Lemieux, VectorBlox Computing Inc.
3:00pm Keystone: An Open-Source Secure Enclave for RISC-V Processors Dayeol Lee, UC Berkeley
3:30pm Introducing New 64GC IP in the SCRx Family of the RISC-V Compatible Cores by Syntacore Alexander Redkin, Syntacore
3:30pm Panel: Challenges and Opportunities for Accelerating Innovation with RISC-V
3:30pm SiFive TERP: A Trusted Execution Reference Platform for Embedded Secure Applications Palmer Dabbelt and Nathaniel Graff, SiFive
4:00pm Design and Implementation of a RISC-V ISA-based In-order Dual Issue Superscalar Processor Libin TT and S. Krishnakumar Rao, C-DAC
4:00pm Machine-Readable Specifications of RISC-V ISA Alexander Kamkin and Andrei Tatarnikov, ISP RAS
4:25pm Ara: 64-bit RISC-V Vector Implementation in 22nm FDSOI Fabian Schuiki and Matheus Cavalcante, ETH Zurich
4:25pm Establishing a Security Verification Framework For The RISC-V Architecture Jason Oberg, Tortuga Logic
4:25pm Secure Bootstrapping of Trusted Software in RISC-V Ilia Lebedev, MIT


Thursday, Dec. 6, 2018 RISC-V Summit Day 3, Member Meetings

Time Event
8:30am Registration & Networking
9:30am RISC-V Task Group Meetings
12:30pm Lunch
1:30pm RISC-V Task Group Meetings


The technical tracks, presented by members of the RISC-V community, will focus on Open RISC-V Platforms, RISC-V Accelerators and Security in RISC-V. For more information on each track, please see below:

Tuesday, Dec. 4, 2018:

Wednesday, Dec. 5, 2018:


The Summit’s Exhibit Hall will be open at the following times to showcase RISC-V-based product demonstrations and allow attendees to explore the latest innovations on the market:

Tuesday, Dec. 4, 2018:

  • 10:20 a.m. – 1 p.m. PST
  • 1:10 p.m. – 3:10 p.m. PST

Wednesday, Dec. 5, 2018:

  • 9:55 a.m. – 11:55 a.m. PST
  • 1:25 p.m. – 3 p.m. PST


Promotional pricing for the three-day Conference and Exhibition Pass is available until Monday, Oct. 29. Platinum, Gold and Silver level members of the RISC-V Foundation qualify for discount codes. Please contact for your member discount code. To learn more about the packages and limited-time promotions, please visit:

Sponsorship packages, media partnerships and exhibition packages are also available, see details here. For press interested in attending, please email: to receive your complimentary pass.