Join us at the Embedded World 2019 Exhibition & Conference from Tuesday, Feb. 26 to Thursday, Feb. 28, 2019 at the NürnbergMesse in Nuremberg, Germany.
Visit Our Booth Featuring Seven Member Companies
The RISC-V Foundation booth will feature pods from member companies Andes Technology, CloudBEAR, GreenWaves Technologies, Imperas Software, SiFive, Syntacore and UltraSoC. Visit us in Hall 3A, booth 3A-536.
Check Out Our Members’ Booths
Additional RISC-V member companies will be located at the following booths:
- AdaCore – Hall 4 / 4-149
- Antmicro – Hall 4A / 4A-621
- Ashling Microsystems – Hall 4 / 4-107
- Cobham – Hall 3A / 3A-518
- Cortus – Hall 3 / 3A-601
- IAR Systems – Hall 4 / 4-216
- Microchip Technology – Hall 1 / 1/500 & 1-510
- NXP – Hall 4A / 4A-220
- Silex Insight – Hall 4A / 4A-100
- SYSGO – Hall 4 / 4-534
- TRINAMIC Motion Control – Hall 3 / 3-511
- Western Digital – Hall 3A / 3A-429
Take Part In Our Scavenger Hunt To Win Prizes
We’ll also be hosting a fun scavenger hunt! You can find the scavenger hunt form at the RISC-V Foundation booth (Hall 3A, booth 3A-536). To participate, visit each of the pods in the RISC-V Foundation booth and the booths of our the participating member companies: AdaCore, Antmicro, Ashling Microsystems, Cortus, IAR Systems, Microchip Technology, NXP, Silex Insight, Silicon Labs, SYSGO, TRINAMIC Motion Control and Western Digital.
At each booth, please speak with a company representative to receive a RISC-V sticker. Return your completed passport form to the RISC-V Foundation booth and share your business card to be entered to win one of the grand prizes. Winners will be selected each day; participants must be able to pick up prize from the RISC-V Foundation booth during the duration of the show.
Stop by the RISC-V Networking Event & Happy Hour
Join us at the RISC-V Foundation booth to network with RISC-V enthusiasts and enjoy happy hour drinks on Tuesday, Feb. 26 and Wednesday, Feb. 27 from 17:00 to 18:00 CET. The scavenger hunt prize drawings for the first two days of the show will take place at the happy hour events.
Attend RISC-V Speaking Sessions
Throughout the show, the RISC-V Foundation booth will feature talks from: Andes Technology, CloudBEAR, GreenWaves Technologies, Imperas Software, RISC-V Foundation, SiFive, Syntacore and UltraSoC.
Additionally, the main conference program will feature a number of RISC-V talks. On Feb. 26, there will be a three-part RISC-V series: RISC-V I Overview, RISC-V II Security and RISC-V III System. On Feb. 27, there will be several sessions on RISC-V, including a RISC-V Workshop and panel with several industry experts. Read on to check out the details for each session.
Conference Program: RISC-V Sessions on Feb. 26
Session 5.1: RISC-V I Overview
RISC-V; Practical Industry Approach to Getting Started with This TechnologyWhen: 9:30 – 10 CET
Who: Robert Oshana, NXP Semiconductors
RISC-V is an open hardware ISA. It’s gaining a lot of traction in the industry. Many companies are now asking how to start the process to deploy this technology into their existing organizations. There are many subtle differences when deploying an open architecture and possibly implementation into an organization. There are many parallels to the open source software movement but also differences. In this talk we will discuss some options for deploying RISC-V into industry design flows, both hardware and software, and some tips and tricks for getting starting with this technology.
How to Benefit from RISC-V Based Linux for Embedded Industrial ApplicationsWhen: 10:00 – 10:30 CET
Who: Krishnakumar R, Microchip Technology
RISC-V provides numerous advantages for the embedded and industrial market. These are the facts that (1) the number of instructions are few, that (2) the instruction set is frozen, that (3) Linux is upstreamed and that (4) the RTL can be inspected. -With fewer instructions, the area and power consumed by a RISC-V solution will be less than comparable processor architectures. This leads to system level cost savings for customers. -Because the instruction set is frozen, software investments will be protected. Engineers can write code and it will run on any RISC-V core, forever. Long term product support is assured by RISC-V. -With the majority of embedded and industrial applications using Linux, now that RISC-V supports Linux, customers are free to ignore the ISA and instead choose an architect that best meets their needs. -Some industrial applications have stringent certifications. Many times the choice for processors is very limited. With RISC-V the RTL can potentially be provided, thus shortening certification times and as a side benefit trust can be ensured. How to get started and utilize Linux based RISC-V architectures will be discussed.
The Soul of a New SoC: Hands-on Experience with Embedding a RISC-V CoreWhen: 10:30 – 11 CET
Who: Onno Martens, Trinamic Motion Control Gmbh & Co. KG
RISC-V is an open instruction set architecture which is increasingly gaining interest in the research & open-source community and offers a lot of advantages. With a RISC-V ISA implementation, designers can develop their own processor system and maintain production of developed parts over process or PLD lifetimes as RTL sources can be easily transferred. Moreover, RISC-V offers a lot of optimization options like implementation of custom instructions and scalable architectures. The RISC-V ISA is competing with ARM, especially in low volume industrial applications. With the embedding of a processor into a mixed signal IC for motor and motion control, highly integrated motor controllers can be designed. By doing so, the former motor driver is augmented to an intelligent and self-monitoring motor control solution. In this paper, the process of embedding a RISC-V core into a hardware design is described. The decision process and all greater implementation decisions are explained. Tradeoffs had to be made in several design areas, starting from the feature set of the core followed by its frequency and the additional clock domains. Chip size was mainly influenced by the size of NVM and SRAM. IP was bought to shorten development time. Analog circuitry enlarged the product to a unique product. Standard peripherals optimized for motion control make the product highly flexible. Practical learnings are presented as well as the developed product and the roadmap that came up during development.
Methodology for Implementation of Custom Instructions in the RISC-V ArchitectureWhen: 11:30 a.m. – Noon CET
Who: Larry Lapides, Imperas Software
One of the key advantages of the new RISC-V Instruction Set Architecture (ISA) is that SoC designers are able to add custom features to the ISA to support their specific applications. There are some risks to doing this, both business and technical, plus there is a need to be able to analyze and optimize the customizations. One approach to customization of RISC-V cores is to use correct-by-construction tools to generate both the compliant and custom pieces of the processor. A second approach is to implement the custom features directly in RTL. With both approaches to implementation, there is still the need for both compliance testing and analytical feedback to enable optimization of the customizations. This paper discusses the alternatives for implementation, and describes an instruction accurate virtual platform methodology for compliance testing and architecture exploration. In this methodology, there is an existing parameterized model of the RISC-V ISA specification, and the custom features are added in an external library. This has the advantage of providing a well-verified compliant model, while at the same time enabling the use of the software debug, analysis and test tools in the virtual platform environment. A case study involving the addition of custom security functionality to a 32-bit RISC-V core is presented, including the compliance testing, memory analysis, function and instruction profiling including timing estimation.
Compliance Methodology and Initial Results for RISC-V ISA ImplementationsWhen: Noon – 12:30 CET
Who: Lee Moore, Imperas Software
For most instruction set architectures (ISAs), compliance to the ISA specification is a given. Since all the SoC designers license the RTL from a single source, the RTL complies with the ISA. Similarly the processor IP vendors produce a tool chain to support their ISAs: no compliance issue. Single source provides for consistency, so ecosystems flourish. With the new, open standard RISC-V ISA, the compliance situation is different, because there is no single IP vendor. Compliance testing therefore has become mission-critical for the RISC-V ecosystem. For other ISAs compliance testing has been done by the processor IP vendor, and as a result methodologies and tools for compliance testing have been kept internal, and are not readily available to the industry. This paper introduces the methodology for compliance testing of RISC-V products. The technical issues of determining compliance with the RISC-V ISA are discussed. These issues include providing a framework for development of additional tests, the development of the tests themselves and reference models. Further issues include how to enable users to target the tests at the particular combination of the RISC-V specification subsets that is being used. The questions of completeness and specification coverage are discussed. Use cases are examined, including testing compliance on various proprietary RTL designs, open source RTL designs, FPGAs, SoCs, ISS models and software tools, with issues experienced being explained.
Session 5.2: RISC-V II Security
Maintaining Security in a Heterogeneous and Changing WorldWhen: 14:30 – 15:00 CET
Who: Jon Geater, Jitsuin and Cesare Garlati, prpl Foundation
Embedded systems are only secure until they’re not. While approaches for secure device provisioning have been around for well over a decade, ways of keeping devices patched and up to date are harder to come by – especially when operating cost enters the fray. So far the most promising approaches for secure device management are heavily silo’d and reliant on proprietary agents and cloud services. These work in limited circumstances but this vendor-centric approach doesn’t scale to the real world of heterogeneous deployments, critical infrastructure and long-term support requirements. A new interoperable approach is needed. To address these points, prpl Foundation Chief Technologist Cesare Garlati will be joined on stage by Jon Geater, CTO at Thales and ex Chair of the GlobalPlatform Security Task Force. Garlati and Geater will share with the audience their practitioner’s experience securing real word embedded applications. In particular, the two industry veterans will explain the common factors, considerations and technical options for running a truly trustworthy heterogeneous network of embedded devices and the best practices developed by their respective organizations to successfully implement security open standards. This session will provide essential learnings for attendees looking to pick through the marketing hype to gain real actionable insight into open standards for establishing and maintaining security across heterogeneous hardware/software architectures.
A New Zero-Trust Model for Securing Embedded SystemsWhen: 15:00 – 15:30 CET
Who: Chris Conlon, wolfSSL and Cesare Garlati, prpl Foundation
Building on the great interest generated last year, Cesare Garlati – Chief Technologist a the non-profit prpl Foundation, is back to the Embedded World Conference to discuss in detail the new components of the open source prplSecurity Framework 2.0. Garlati will begin by analyzing the aspects of embedded computing that contribute to the majority of security incidents. These include proprietary ‘security-by-obscurity’, the complexity associated with proper implementations of modern connectivity stacks, the lack of a root of trust anchored in hardware, and the intrinsic promiscuity of code and data within embedded system. Garlati will then propose a set of new APIs to overcome these challenges, as advocated by the prpl Foundation. The prplSecurity Framework 2.0 is a comprehensive set of open source APIs designed to provide end-to-end security silicon-to-cloud. Key aspects include: – An overall open source approach in contrast to the old myth of ‘security by obscurity’ – A secure boot API to execute code cryptographically signed by a trusted entity. – Physically Uncloneable Functions (PUF) APIs to create a root of trust in silicon. – A Trust Continuum API to maintain trust throughout the whole life cycle of the device. – A micro hypervisor to create multiple hardware-enforced security domains on the chip. The presentation will be essential viewing for system designers and application developers with an interest in innovative, yet practical, ways to secure embedded system applications.
Session 5.3: RISC-V III System
User Mode Interrupts: a Must for Securing Embedded SystemsWhen: 16:00 – 16:30 CET
Who: Prof. Sandro Pinto, Universidade do Minho and Cesare Garlati, prpl Foundation
All modern processor architectures define some levels of privilege to support secure system design. However, servicing interrupts with high privileged code completely breaks the security model. So, what should a security-conscious designer do? Is a system really secure if interrupts aren’t secure? Real time operating systems, runtime frameworks, peripheral drivers, 3rd party libraries: they all have interrupts handlers that are not verified or proprietary – which likely means not verifiable. How do you build a trusted computing model when potentially untrusted code has high privilege access through its interrupt handlers? In this workshop, industry veteran Cesare Garlati – Chief Security Strategist at the non-profit prpl Foundation, uncovers the problem of securing interrupts in embedded systems and introduces an innovative approach to interrupt security that doesn’t require specific hardware extensions. Robust solutions to interrupt security are presented for three different scenarios: traditional monolithic code base, dual-world implementation – similar to ARM’s TrustZone, and a multi-domain trusted execution environment. This workshop is a must-attend for system designer and embedded developers who understand the risk of unsecured interrupt handlers but can’t afford to switch to a platform that provides built-in support or extensions for user-mode interrupts.
Embracing a System Level Approach: Combining Arm & RISC-V in Heterogeneous DesignsWhen: 16:30 – 17:00 CET
Who: Rupert Baines, UltraSoC
The open RISC-V CPU architecture is gaining substantial market traction; the ecosystem’s focus is moving from legacy/incumbent processor-centric thinking to system-level issues. Part of that move is a growing realization that many, if not most, designs will include RISC-V in addition to other CPUs and GPUs. Issues of heterogeneous design therefore become key architectural considerations. In addition there needs to be an infrastructure that supports the co-existence of legacy subsystems with new ones such as those implemented using RISC-V. A “system on chip” should be developed as system: not as though it were a collection of independent pieces. This presentation will look at these issues and how they can be addressed. We will provide specific examples, focusing particularly on designs that combine RISC-V and Arm processors within the same SoC.
RISC-V: High Performance Embedded SweRV Core Microarchitecture, Performance and Implementation ChallengesWhen: 17:00 – 17:30 CET
Who: Dr. Zvonimir Bandic, Western Digital
RISC-V: high performance embedded SweRV core microarchitecture, performance and implementation challengesRISC-V Instruction Set Architecture (ISA) has become a key driver of open source hardware projects. Most recently we have for example seen a lot of applications in the Internet of Things (IoT), microcontrollers for a variety of traditional embedded applications, and applications requiring capability for low power operation of Artificial Intelligence (AI) inference engines based on artificial neural networks. We have developed a super-scalar (2-way), 9-stage pipeline, mostly in-order, open-source core based on the RISC-V RV32IMC instructions set, named SweRV. It initially targets in-house embedded Storage System on Chip applications. We present some of the architectural details of the core and implementation challenges, as well as discuss application of the core for the Flash controllers. We also report performance measurements of Coremark and Dhrystone benchmarks, which are traditionally used for embedded core performance benchmarking. In addition to the SweRV core, we have also developed a SweRV Instruction Set Simulator (ISS). We present some of the details of the simulator, including performance numbers. Some of the implementation challenges that we have encountered were related to the tradeoff of code density and performance of RISC-V. We report our initial findings and code density improvement solutions based on compiler and linker optimizations.
Presentations Exhibitor´s Forum
The Future of FreeRTOSWhen: 14:30 – 15:00 CET
Who: Richard Barry, AWS Amazon Web Services, Inc. and Rick O’Connor, RISC-V Foundation (intro)
The open source (now MIT licensed) FreeRTOS kernel has helped embedded developers manage the complexity of their microcontroller designs for 15 years – during which time FreeRTOS has gained a reputation for reliability, ease of use, and responsive support. Under the stewardship of Amazon Web Services (AWS), the FreeRTOS project has expanded to include MIT-licensed security and connectivity libraries. In this presentation Richard Barry, the founder of the FreeRTOS project, will announce what’s next for FreeRTOS, including AWS involvement in open source projects. Join us for this session and find out first.
How to Build a RISC-V Embedded System In Just 30 MinutesWhen: 9:30 – 10:30 CET
Who: Cesare Garlati, prpl Foundation and Drew Barbier, SiFive
The impressive growth of the RISC-V ecosystem is on everyone’s lips. Originally developed at UC Berkeley, the free and open ISA promises to bring the innovation and collaboration of the open source community to the hardware world – and to dramatically disrupt the whole semiconductor industry in the process. However, hardware and software engineers used to traditional closed-source proprietary architectures and tools may find difficult to orient themselves in this highly-fragmented galaxy of RISC-V technologies, open source tools and development frameworks. So really the question is: How do I get started with RISC-V? In this class, industry veteran Cesare Garlati – long-time member of the non-profit RISC-V Foundation, will show exactly that: how to download, build, configure, debug and test a completely free and open source RISC-V development environment. Specific step-by-step instructions presented in this class – all free / open source: – program the FPGA with a fully customizable RISC-V softcore (Rocket) – build the RISC-V GNU toolchain – both 32bit and 64bits – build the OpenOCD / JTAG debug stack – configure the Eclipse IDE with the RISC-V embedded development plugin – develop, compile, debug and test on actual hardware your first RISC-V “Hello World” application This class is a must-attend for SoC designers, system architects, and software developers who want to get started with RISC-V development but have no time to figure out and assemble all the necessary moving parts.
How to Secure a RISC-V Embedded System In Just 30 MinutesWhen: 10:30 – Noon CET
Who: Cesare Garlati, prpl Foundation and Don Barnetson, Hex Five Security
Originally developed at UC Berkeley, the free and open RISC-V ISA promises to bring the innovation and collaboration of the open source community to the hardware world. When it comes to security, RISC-V specifications provide many important building blocks. And the highly fragmented RISC-V ecosystem even more. For designers used to traditional closed-source proprietary architectures, the complexity associated with properly implementing these new security technologies may prove daunting. So really the question is: How do I properly secure a RISC-V embedded system? In this class, industry veteran Cesare Garlati – Chief Security Strategist at the non-profit prpl Foundation and long-time member of the RISC-V Security Group, will show exactly that. Specific step-by-step instructions presented in this class – all free / open source on GitHub: – develop a secure embedded application with front-end, Root of Trust and Secure Boot functions – install and configure a multi-domain Trusted Execution Environment – “plug-in” the functions to the Trusted Execution Environment – flash the resulting firmware to an actual FPGA board running a RISC-V Rocket core – run the complete application and demonstration the overall safety and security of the system This class is a must-attend for SoC designers, system architects, and software developers who want to properly implement secure RISC-V systems but don’t want to take the time and the risk of figuring out the necessary moving parts themselves.
Trusted Execution Environments: A System Design PerspectiveWhen: Noon – 12:30 CET
Who: Cesare Garlati, prpl Foundation and Boran Car, Hex Five Security
The RISC-V open ISA provides many key building blocks of security, but assembling these into a robust embedded system requires a team of security experts – and a very unique mindset too, often labeled as “paranoid”. Unfortunately, the complexity associated with properly implementing some of these – admittedly esoteric – technologies often results in them not being used at all. In this workshop, industry veteran Cesare Garlati – Chief Technologist at the non-profit prpl Foundation and key member of the RISC-V Security Group, comes to the rescue to shows step-by-step design and development of a multi-domain Trusted Execution Environment applied to a real-world embedded system. Garlati will start with programming the open source bitstream of a Rocket core into a commercial FPGA. He will then partition the system into a set of equally secure trusted execution environments. Garlati will then “drop” front-end, authentication and critical backend control applications into separate application domains. He will conclude by formally verifying the security of the overall system: the components of the system are reviewed in the detail as is the required test coverage to gain confidence in the implementation. SoC architects and system designers are left with a framework and a template for utilizing the building blocks defined in the RISC-V ISA to develop real-world security solutions.
Conference Program: RISC-V Sessions on Feb. 27
Class 5.2: RISC-V Workshop
Opportunities and Risks in Open Source ProcessorsWhen: Noon – 13 CET
Who: Cesare Garlati, prpl Foundation; Markus Levy, NXP Semiconductors; Tim Whitfield; Arm; Ted Marena, Western Digital
The project began back in 2010 at the University of California, Berkeley, and is already being co-developed and promoted by hardware and software developers worldwide, including leading semi-conductor manufacturers. In addition, a large community has formed for the development of the ecosystem around the CPU architecture. The panel discussion will not only look at the latest state of the art but will also explore the benefits and drawbacks of these kinds of open architectures.
Four established international experts will debate the topic of RISC-V in a discussion moderated by Frank Riemenschneider, editor-in-chief of the specialist journal Design & Elektronik. They are Cesare Garlati, Chief Security Strategist, prpl Foundation, Markus Levy, Head of AI and Machine Learning Technologies, NXP Semiconductors, Ted Marena, Director, RISC-V Ecosystem, Western Digital and Tim Whitfield, VP Strategy, Embedded and Automotive, Arm.
Professor Axel Sikora, chair of the advisory committee of embedded world and the embedded world conference, is looking forward to the panel discussion: “RISC-V is a hot topic, because comparable to the battle between Linux and Microsoft, an attempt is being made to challenge the market position of Arm. The discussion at the forum with top-class international players is sure to be very interesting. For those who want to delve a little deeper into the technology, the conference will also devote one and half days to presentations and classes exclusively on RISC-V.”
Session 6.3: Software Engineering II Design & Modeling
Design Cycle Acceleration for Hardware/Software Co-Design with RenodeWhen: Noon – 12:30 CET
Who: Steve Milburn, Dover Microsystems and Michael Gielda, Antmicro Ltd.
Embedded systems design that involves “whole stack” co-design, including hardware, firmware, runtime (OS), and development toolchain, presents novel engineering challenges. Traditional hardware-led approaches do not work, as the software and toolchain need to co-evolve with the hardware. Complex tradeoffs around where in the stack to implement functionality and to optimize require hardware-software co-design. Dover Microsystems faced such challenges when implementing a cybersecurity product that involves both silicon IP and runtime & toolchain modifications. Dover is using the Renode open source functional simulation framework to drastically reduce their design cycle, rapidly explore architecture trade spaces, and engage in hardware/software co-design. In addition, the approach enables Dover to provide a simple and effective means for customers to evaluate the entire solution, and to begin adapting their software collateral in parallel with the hardware integration effort. Renode is backed by professional support from Antmicro, the creators of and primary contributors to Renode, whom Dover contracted to extend the framework with features necessary for their – and their customer’s – use cases. Antmicro and Dover Microsystems will jointly present a case study of how open-source, extensible, debuggable, and robust functional simulation has been critical to Dover’s success, and why it should become a standard part of all hardware and embedded system design and development efforts.