The RISC-V Association (RVA), an interim community formed by employees from RISC-V Foundation members, is hosting the RISC-V Day Tokyo on Sept. 30, 2019 at the Hitachi Baba Hall in Kokobunji, Tokyo from 9 a.m. – 8 p.m. JST. During the event, the speakers will cover a variety of topics such as lowering the barrier to silicon, edge server security, open source CPU and subsystem, open source EDA tools, and IoT server infrastructure. They will also discuss the future of RISC-V and its solutions for security applications. Foundation members Symbiotic EDA, Hitachi and Sony will be presenting at the event and several members will also be sponsoring the event, including Western Digital, Andes Technology, Syntacore, IAR Systems and SiFive. The RISC -V Foundation’s CEO Calista Redmond will be speaking at the event as well with her presentation, “Global Importance and Momentum of RISC-V”.
To register, attendees must RSVP on the Meetup page and purchase tickets here. The prices are detailed below:
- General admission: $35 or 4000 yen
- Student admission (excluding PhD students): $10 or 1500 yen
- Reception: $20 or 2500 yen
Learn more about the event at the RISC-V Association website here.
RISC-V Day Tokyo
| Global Importance and Momentum of RISC-V | RISC-V Foundation CEO Calista Redmond (USA) |
| Expanding Innovations (Tentative Title) | Hitachi Ltd., Central Research Laboratory, General Manager Yuichi Yagawa |
| The Future Created by Big Data in Cars and Edge Computing | Toyota Automotive, Project General Manager Kenichi Murata |
| Red Hat Participation in RISC-V, Fedora and Firmware Development | Red Hat, Software Engineer Wei Fu (USA) |
| Future of open source EDA tool for FPGA and SoC | Symbiotic EDA CEO Edmund Humenberger (Austria) |
| The Arrival of Humanity Computing -Prospects and Unlimited Potentials for RISC-V- |
Ghelia Inc., CEO Ryo Shimizu |
| NEDO RISC-V AI Edge Security Project Introduction | NEDO Project Members Hitachi, Keio, AIST, etc. |
| VDEC, AI Design Center and RISC-V | Professor, University of Tokyo Makoto Ikeda |
| Taking RISC-V from Edge to Cloud | Andes Technology, CTO Charlie Su (Taiwan) |
| IAR Embedded Workbench compiler for RISC-V | IAR, Marketing Manager Masaru Furue (Sweden) |
| SCR Series RISC-V MCU/CPU | Syntacore Alexander Redkin（Russia） |
| Fuji Soft RISC-V Security Solution | Fujisoft Peng Liu |
| Embracing a system level approach in the real world: combining ARM and RISC-V in Heterogeneous Designs | UltraSoC CEO Rupert Baines（UK） |
| Automatic Compiler Generation for RISC-V ISA Customization | Codasip Tomonari Tohara（Czech Republic） |
| Innovation Unleashed: Solutions and Silicon Enabling the Intelligent Edge and Linux (Tentative Title) | SiFive TBD (USA) |
| Russian MCU / CPU History: How did we come to adopt RISC-V? | Cloudbear Alexander Kozlof（Russia） |
| Greeting from RISC-V Foundation Member Company Representatives | Sony LSI Design Vice President Hideki Yoshida |