Join us at the Embedded World 2020 Exhibition & Conference from Tuesday, Feb. 25 to Thursday, Feb. 27, 2020 at the NürnbergMesse in Nuremberg, Germany.
Visit Our Booth Featuring Fourteen RISC-V Members
The RISC-V Foundation booth will feature fourteen pods from RISC-V members Andes Technology, CHIPS Alliance, CloudBEAR, Codasip, Embecosm, GreenWaves Technologies, Imperas Software, Intrinsic ID, OneSpin Solutions, OpenHWGroup, SiFive, Syntacore and UltraSoC. Visit us in Hall 3A, Booth No. 3A-536.
Check Out Our Members’ Booths
Additional RISC-V members will be located at the following booths:
- AdaCore – Hall 4 / 4-149
- Antmicro – Hall 4A / 4A-621
- Cadence – Hall 4 / 4-126
- Cortus – Hall 3 / 3-634
- GigaDevice Semiconductor – Hall 4A / 4A-300
- IAR – Hall 5 / 5-340
- Lauterbach – Hall 4 / 4-210
- Nordic Semiconductor – Hall 4A / 4A-310
- Qualcomm – Hall 4A / 4A-330
- Segger – Hall 4 / 4-238
- Silex Insight – Hall 5 / 5-366
- Silicon Labs – Hall 4A / 4A-128
- Think Silicon – Hall 3 / 3-764
- Trinamic – Hall 3 / 3-253
- VeriSilicon – Hall 4A / 4A-360
- Wind River – Hall 5 / 5-324
Take Part In Our Scavenger Hunt To Win Prizes
The RISC-V Foundation will also be hosting a fun scavenger hunt! You can find the scavenger hunt form at the RISC-V Foundation booth (Hall 3A, Booth No. 3A-536). To participate, visit each of the pods in the RISC-V Foundation booth and the booths of our participating RISC-V Foundation members: Antmicro, Cortus, IAR, Trinamic and VeriSilicon.
At each booth, please speak with a company representative to receive a RISC-V sticker. Return your completed passport form to the RISC-V Foundation booth and share your business card to be entered to win one of the grand prizes. Winners will be selected each day; participants must be able to pick up their prize from the RISC-V Foundation booth during the duration of the show.
Join us for the RISC-V Networking Event & Happy Hour
Join us at the RISC-V Foundation booth to network with RISC-V enthusiasts and enjoy happy hour drinks on Tuesday, Feb. 25 and Wednesday, Feb. 25 from 17:00 to 18:00 CET. The scavenger hunt prize drawings for the first two days of the show will take place at the happy hour events.
Attend RISC-V Speaking Sessions
Throughout the show, the RISC-V Foundation booth will feature talks from the following:
- Andes Technology
- CHIPS Alliance
- CloudBEAR
- Codasip
- Embecosm
- GreenWaves Technologies
- Imperas Software
- Intrinsic ID
- OneSpin Solutions
- OpenHWGroup
- SiFive
- Syntacore
- UltraSoC
Additionally, the main conference program will feature a number of RISC-V classes and sessions. Read on to check out the details for each session.
Conference Program: RISC-V Classes and Sessions on Feb. 25
CLASS 5.1: How to Secure RISC-V and Cortex-M Embedded Applications (Feb. 25)
- How to Build & Secure a RISC-V Embedded System
- When: 14:30 – 16:00 CET
- Who: Cesare Garlati, Hex Five Security; Prof. Sandro Pinto, Universidade do Minho
- Location: Conference Counter NCC Ost
SESSION 10.3: SoC III – Tools & Verification (Feb. 25)
- Impact of RISC-V Adaptability on SoC Verification Methods
- When: 14:30 – 15:00 CET
- Who: Simon Davidmann, Imperas Software
- Location: Conference Counter NCC Ost
- Verification of RISC-V SoC Designs Using Formal Methods
- When: 15:00 – 15:30 CET
- Who: Sven Beyer, OneSpin Solutions
- Location: Conference Counter NCC Ost
SESSION 3.2: II Embedded OS IV – Linux II (Feb. 26)
- A Clean Slate Approach to Embedded Linux Security: RISC-V Enclaves
- When: 17:00 – 17:30 CET
- Who: Cesare Garlati, Hex Five Security
- Location: Conference Counter NCC Ost
SESSION 10.4: II SoC V – System Technology II (Feb. 26)
- An Enclave-based TEE for SE-in-SoC in RISC-V Industry
- When: 15:00 – 15:30 CET
- Who: Vincent Cui, T-HEAD Semiconductor Inc. / Alibaba Group
- Location: Conference Counter NCC Ost
Exhibitor Forum (Feb. 26)
- Introducing the World’s First RISC-V based MCU – GD32VF103x
- When: 13:00 – 13:30 CET
- Who: Reuben Townsend, GigaDevice Semiconductor Inc.
- Location: Exhibitor Forum, Hall 3A, 3A-730
SESSION 5.5 Hardware V – Architectures (Feb. 27)
- Leveraging the Scalability of the RISC-V ISA to Create Optimized MCU Designs
- When: 13:30 – 14:00 CET
- Who: Yunsup Lee, SiFive Inc.
- Location: Conference Counter NCC Ost
- The ParaNut/RISC-V Processor – An Open, Parallel, and Highly Scalable Processor Architecture for FPGA-based Systems
- When: 14:30 – 15:00 CET
- Who: Alexander Bahle, University of Applied Sciences Augsburg
- Location: Conference Counter NCC Ost
- A Cycle-accurate Trace Approach for RISC-V Systems
- When: 16:00 – 16:30 CET
- Who: Gajinder Panesar, UltraSoC
- Location: Conference Counter NCC Ost
Learn More
You can check out the full Embedded World program here. To schedule a meeting with the RISC-V Foundation or a member organization, please email: RISC-V@racepointglobal.com.
Stay up-to-date about the latest RISC-V news by following the RISC-V Foundation on LinkedIn, Twitter and YouTube.