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Voting is open for the election of RISC-V International Strategic and Premier TSC and Community representatives on the RISC-V Board of Directors!
Voting will take place through July 27, with new representatives announced July 22. You can self nominate using the form below and eligible candidates will be featured on this page starting from May 23. The following seats will be elected:
- 3 Director representatives for Strategic & Premier TSC members
- 1 Director representative for Community Organization members
- 1 Director representative for Community Individual members
Board membership is an important responsibility. Elected Directors are members of and vote on behalf of their respective membership tier. Directors are expected to attend all board meetings, which are currently held at 7am Pacific time on the third Thursday of each month. At these meetings, they will represent the other RISC-V members at their level in discussions as well as votes, and will make themselves available for regular communication with the other members at their level. Representatives will vote on behalf of their membership tier, not for their specific companies. For more guidance on board member expectations and requirements, see Article 1 of the Internal Regulations.
Each board seat lasts for two years, provided that the Director’s organization remains a member in good standing during that time. All members of RISC-V International in good standing between June 23 – July 21 may vote on the nominations. Ballot links will be sent to the voting member of record. Each member may vote only once. For those members unable to vote using this method, we can accommodate votes by email. Please note that nominations and votes can only be recorded by members of RISC-V International.
These are the important dates for this election:
- May 1: Call for Nominations announced and opened
- May 23 – June 22: Nominations posted and closed on 6/22
- June 23 – July 27: Ballots sent to members, open for voting (Voting closes at 9am PDT on July 27)
- July 27: Announce newly elected Board members, term to initiate officially 8/1
- August 1: Effective date for newly elected Board members
Please contact the program managers at elections@riscv.org with any questions.
Nominees: Representatives for Strategic & Premier TSC Members (3 seats)
Wei Wu
Project Director of PLCT Lab
Institute of Software, Chinese Academy of Sciences
Wei Wu is the founder and project director of the PLCT lab, ISCAS. Improving the software ecosystem for RISC-V has been set as one of the most important strategic objectives of PLCT lab. His team maintains a series of key open source infrastructure such as OpenJDK RISC-V backend, V8 RISC-V backend, Spidermonkey RISC-V JIT backend, LuaJIT RISC-V downstream implementation, as well as GNU Toolchain, Clang/LLVM RISC-V backend. The TARSIER project he launched at the end of 2021 has taken a big step forward in RISC-V desktop computing and Linux distribution support. He is the ISCAS representative at RVI TSC and the chair of ISA Infrastructure Horizontal Committee.
Wei Wu launched a more ambitious plan in February 2024: the Jiachen Project. The mission of the plan is to cover all information industry fields with RISC-V within 12 years and obtain support from all major commercial software products. This is Wei Wu’s latest effort to promote and improve the RISC-V software ecosystem.
Wu Wei has served as a director of the LLVM Foundation Board of Directors (BoD) since 2022, and is committed to maintaining the healthy development of the LLVM community, improving LLVM infrastructure, and attracting more groups to join the LLVM developer community. Additionally, he serves as a director of the CHIPS Alliance Foundation.
Wei Wu is very passionate about educating RISC-V to engineers and amateurs. He often gives talks and lectures among amateurs and college students in local meetups. He also collaborates with college teachers, providing RISC-V software lectures and experiment courses.
Ted Speers
Technical Fellow
Microchip Technology
Biography:
I am a Technical Fellow at Microchip’s FPGA BU, where I am responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. I joined Actel (now part of Microchip) in 1987 and have held roles in process engineering and product engineering before assuming my current role in 2003. I am a co-inventor on 35 U.S. patents. In my role, I have consistently defined first of its kind products, the most recent example being PolarFireSoC, the first RISC-V based SoC FPGA. Prior to joining Actel, I worked at LSI Logic. I have a Bachelor of Science in chemical engineering from Cornell.
Extended nomination comments regarding upcoming director vote:
To the RISC-V Board of Directors,
I’d like to congratulate Ken and Jefro on their election. There are few who can match their service to and impact on RISC-V.
Those few include both Philipp and Roger. No matter, the outcome of this vote, the RISC-V Board will be in good shape.
I’m happy with my original nomination statement (below) but I thought I’d take the time to provide some more context and make a more personal appeal.
Let’s start with the personal appeal. The reason you want me is that I’m different, in a lot of ways, most of them good. I’ll try to highlight two of those which I believe many of you can personally vouch for.
- I have vision and, more than that, I have a track record of making vision a reality. I’ll touch on an example later when I discuss commercialization.
- I’m collaborative. Collaboration includes helping everyone find their voice and being a trusted arbiter known for considering all sides. Members have come to me to help resolve disputes with other members. I reached out to new board members who joined just as we entered Covid and helped them understand the dynamics of board meetings. While I certainly represent the ‘old guard’ on our board, I have embraced and supported the skills and priorities of the newer members who are helping us evolve to the next level.
Regarding commercial impact, I could make a long list of RISC-V firsts on the road to commercialization and adoption that Microchip can claim. I can point out that Microchip’s exhibitor spend on RISC-V Events has been roughly $500k in just the last 3 years.
I would like to focus on HPSC … High Performance Space Computer ( https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64-hpsc ) . It is an SoC, designed and produced by Microchip, comprising an octal SiFive X280 vector processor. When I first heard of RISC-V in 2015, I thought immediately of its potential in the space market and I’ve been pulling on the space thread since day one. You’ll find a space theme woven into most of my talks.
The first RISC-V commercial IP purchase (and first time RISC-V beat Arm) was for a Microchip FPGA implementation for a satellite payload. In addition to NASA, the European space market has selected RISC-V for future space processors.
I am positive that I have had a significant role in RISC-V capture of the space market. My membership on the board was a big help. I believe my continued participation on the board will enhance the success of RISC-V and the success of HPSC in the space market and in adjacent areas such as safety critical, vector processing, AI, and government affairs.
Finally, you may think that that the space market, while cool, is relatively minor. I play the long game and I have believed that this market will become significant. There is a lot of venture capital going toward the space market and projects such as lunar data centers are being funded. RISC-V is already on the space station running Ubuntu and will be landing on the moon at the end of this year in support of such a venture.
Thank you for your consideration in this upcoming vote.
Ted
Original Nomination Comments:
I have been a RISC-V leader and evangelist and have served on the Board of Directors of RISC-V International since its inception in 2016. I am currently serving my second term as Secretary.
I am proud of my leadership contributions to RISC-V International and to RISC-V in general which include:
As a board member,
– I have been very accessible and have relationships with members across the globe and with all classes of members including adopters, solution providers, academics and influencers.
– I am thought of as one who relates well with new board members, listens to them and helps them promote new perspectives they bring.
– I have played key leadership roles in all phases of our growth starting with evangelization, then execution and now commercialization.
My role as an adopter of RISC-V has made a significant commercial impact.
– The first RISC-V ever shipped in a product is believed to be an implementation in a Microchip FPGA.
– PolarFireSOC FPGA is among the first implementations of RISC-V in commercial silicon.
– Microchip is now building NASA’s High Performance Space Computer (HPSC) which is centered around RISC-V processors with vector extensions.
A key next phase challenge for RISC-V that I can impact during the next term is continued adoption of RISC-V in vertical segments. RISC-V’s success in the space market is transferrable to many domains including AI and automotive.
I would be honored to be elected to continue to serve as your Board representative. Thank you.
Roger Espasa
CEO
SemiDynamics Technology Services
Biography:
Roger Espasa is the founder and CEO of SemiDynamics, an IP supplier of RISC-V
cores supporting the RISC-V vector extension, Tensor Unit extension and
Gazzillion(tm) misses, targeted at HPC and Machine Learning. In addition,
SemiDynamics architected and designed the Esperanto Technologies’ 1024+ core
machine-learning 7nm SoC. Prior to Semidynamics, Roger was at Broadcom working
on an ARMV8 wide out-of-order core (2014-2016). Previously, Roger worked at
Intel (2002-20014) developing a vector extension for the x86 ISA, initially
deployed in XeonPhi (Larrabee) which then became AVX-512. Roger also led the
texture sampling unit for Larrabee. Roger then worked on Knight’s Landing
(14nm) and led the core for Knights Hill (10nm). Between 1999 and 2001 Roger
worked for the Alpha Microprocessor Group on a vector extension to the Alpha
architecture known as Tarantula. Roger got his PhD from UPC in 1997, has
published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D
Architecture, Binary translation and optimization, Branch Prediction, and
Media ISA Extensions and holds 9 patents with 41 international filings.
cores supporting the RISC-V vector extension, Tensor Unit extension and
Gazzillion(tm) misses, targeted at HPC and Machine Learning. In addition,
SemiDynamics architected and designed the Esperanto Technologies’ 1024+ core
machine-learning 7nm SoC. Prior to Semidynamics, Roger was at Broadcom working
on an ARMV8 wide out-of-order core (2014-2016). Previously, Roger worked at
Intel (2002-20014) developing a vector extension for the x86 ISA, initially
deployed in XeonPhi (Larrabee) which then became AVX-512. Roger also led the
texture sampling unit for Larrabee. Roger then worked on Knight’s Landing
(14nm) and led the core for Knights Hill (10nm). Between 1999 and 2001 Roger
worked for the Alpha Microprocessor Group on a vector extension to the Alpha
architecture known as Tarantula. Roger got his PhD from UPC in 1997, has
published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D
Architecture, Binary translation and optimization, Branch Prediction, and
Media ISA Extensions and holds 9 patents with 41 international filings.
Nomination Comments:
I would like to represent the Strategic Members at the Board to keep pushing for RISC-V adoption across geos and markets.
Pedro Lopez Estepa
Managing Director / Head of Market and Business Development
Quintauris
Biography:
Pedro Lopez is the Managing Director of Quintauris, a joint venture from semiconductor industry players Bosch, Infineon, Nordic Semiconductor, NXP® Semiconductors, and Qualcomm Technologies, Inc., aimed at advancing the adoption of RISC-V globally by enabling next-generation hardware development.
Pedro has more than 15 years of automotive market strategy and engineering experience, working extensively with global automotive and automation industries, as well as consortiums and other ecosystem entities as COVESA, SOAFEE, AEVAC or OMG.
Prior to Quintauris, Pedro López was the Director of Automotive at Real-Time Innovations (RTI), the largest software framework company for autonomous systems based on the open-standard DDS. In this position, he leaded RTI’s fast-growing global automotive business and strategy. Pedro joined RTI from u-blox, the Swiss semiconductor leader, where he led automotive market strategy at the short-range business unit.
Pedro holds a MSc in Telecommunications Engineering from the University of Granada and an International Master of Business Administration degree from the Politecnico di Milano.
Nomination Comments*:
I have a vast experience serving in different boards of community organizations such as COVESA, SOAFEE, AEVAC or OMG. If being honored to serve as a member of board, I will commit to guarantee the evolution towards industrialization and expansion in commercial markets. In the role of Managing Director and Head of Market Development at Quintauris, I am in a privilege position to help accelerate the commercialization of reference architectures based on RISC-V, reduce defragmentation, promote competition and nurture the ecosystem.
I am looking forward to contributing to the next phase of RISC-V International offering my expertise in open standards such as VSS or DDS, leveraging my experience in international community organizations. Given my market and engineering background, I believe I can contribute to innovation in both directions. It would be a privilege to serve in the board of such a dynamic and cooperating organization that is revolutionizing the processor ecosystem.
Experience in other organizations:
I am currently a member of the Spanish Association of Autonomous Vehicle (AEVAC) board where he contributes as an expert in Architecture Vehicles and Autonomous Systems. Previously, Pedro served in the board of the Connected Vehicle System Alliance COVESA (previously GENIVI Alliance) where help standardize the core technologies, such as DDS, that help accelerate the future of connected vehicles, while keeping safety and cybersecurity a top priority.
Olof Kindgren
Award-winning engineer
Qamcom
Olof Kindgren
Award-winning engineer
Biography:
I came in contact with RISC-V ten years ago through my work on the Free and Open Source Silicon Foundation and have followed the development ever since. Over the years I have been working on RISC-V through advocacy, being a RISC-V Ambassador since 2020 and organizing RISC-V-related events. I have also done hands-on RISC-V development, most notably as the creator of the award-winning SERV, the world’s smallest RISC-V CPU and VeeRwolf, a RISC-V-based platform that is now used by thousands of students getting their first taste of RISC-V through the RVFPGA computer architecture course.
Comments on why I want to be on the RISC-V Board of Directors:
On the board I would represent Qamcom and hopefully all other SMEs who might not necessarily be making RISC-V CPUs themselves, but have a vested interest in seeing RISC-V succeed within their domains. Working for a company doing cutting edge research and development within e.g. RADAR, 6G, automotive, medtech, functional safety, IoT and ML will provide the domain expertise needed for understanding what it takes for RISC-V to increase its presence in the industry.
Ken Dockser
CPU Architect
Tenstorrent
Biography:
Ken continues to be passionate about RISC-V and all of its potential!
Since 2018 he has actively contributed to the RISC-V community through serving on the Board of Directors and the Technical Steering Committee, heading several Task Groups, authoring several ISA extensions, contributing to many TGs & SIGs, and making multiple presentations at RISC-V Summits and Workshops. In his day job, he has played a key role in the development and optimization of several RISC-V implementations.
Ken is a Senior Principal Architect at Tenstorrent where he defines high-end RISC-V processors and systems.
Ken has over 37 years of experience in computer architecture and development, and has over three dozen patents.
When not helping develop the RISC-V architecture, implementing RISC-V designs, helping develop new floating point standards (IEEE P3109 and IEEE-754), or developing processor benchmarks (SPEC OSG), Ken can be found spending time with family, fiddling with antique phonographs, and playing classical guitar.
Nomination Comments:
When I served on the RISC-V Board in 2020-2021, I worked hard to address the needs and concerns of you, the Strategic and Premier-TSC Members. I welcomed your input and was happy to set up video calls and answer emails. I actively listened to your concerns, answered your questions, and discussed potential solutions that I later brought to the board.
I would like to represent you on the board once again, channeling that same enthusiasm and commitment that I brought previously. I plan to collaborate with other board members to ensure that we channel our efforts into the areas that are key to your success.
Thank you for your support.
Karel Masarik
President and founder
Codasip
Biography:
Karel Masarik led the development of Codasip’s underlying technologies as part of a university technological incubator and then founded Codasip in 2014. Codasip launched its processor development toolset, Codasip Studio, in 2014 and announced its first RISC-V processor core in late 2015. As CEO, he has led the company through several funding rounds and has overseen the company’s international expansion. At the end of 2021, he moved to the position of President with the responsibility for the emerging technologies development in the areas such as safety and security, HPC, or AI/ML, with the strong focus as well on the development of the educational activities as part of the company university program. He is actively participating in EU activities such as drafting of EU Chip Act, and he is working closely with several EU members on the adoption of RISC-V as the industry standard. Earlier he undertook research in the use of architecture description languages and design automation at Brno University of Technology. This included research into hardware/software co-design as well as formal and functional verification of processor designs. He achieved a Ph.D. in Computer Science in 2008.
Nomination Comments:
Having been involved with the RISC-V community since its inception, our company actively participates in numerous RISC-V International Working Groups. As a member of the board, I can contribute to the community in a more formal and strategic capacity. Codasip is evolving into a European RISC-V powerhouse, a unique position we proudly hold. I am eager to offer a European perspective, leveraging my involvement in several European Union projects to better understand and align with EU priorities and those of European OEMs. Although my role has increasingly taken on political aspects in recent years, at heart, I remain an engineer passionate about innovation. I am committed to helping RISC-V expand into new and exciting application areas.
Jeffrey Osier-Mixon
Distinguished Open Source Strategist
Red Hat/IBM
Biography
I have been deeply involved in the RISC-V effort for many years. I worked for RISC-V Foundation, and then RISC-V International, from 2019 to 2021 and oversaw several initiatives on the technical side as well as member management and community development. I was also the board secretary during this time. Since moving over to Red Hat in 2021, I have been an advocate for RISC-V software development within Red Hat as well as in the community – in the past few months I have delivered RISC-V talks and a BoF at three separate events, and also work regularly to support the RISC-V software ecosystem through participation in RISE as the outreach committee chair. As a representative for Strategic members, I would work regularly within the community to gather feedback on current RISC-V board issues to build positive communication and to ensure that Strategic members have a voice on the board.
Comments
I strongly believe in the power of communities to accomplish what individuals can not do by themselves. I have seen this effect many times over with open source communities, and also within the RISC-V community. I would be humbly grateful to bring my expertise with open source to the RISC-V board and to re-engage with the executive community that drives RISC-V’s success, and to be able to contribute back by facilitating communication between Strategic members and the board.
Daniele Gregori
CSO
E4 Computer Engineering
Daniele Gregori is currently Chief Scientific Officer of E4 and IEEE Member No. 97548282.
He obtained his Ph.D. on online control system for LHCb detectors at CERN and worked at the INFN Tier1 Data Centre.
He is an expert in parallel file systems, automation tools, data tiering, HPC configuration and quantum computing systems. He joined the E4 team in 2015, bringing expertise in high performance storage, installation and management. From 2020 he leads the E4 European Projects Department and he is responsible for E4’s contribution to more than 17 European projects dedicated to developing new HPC technologies in the fields of emerging architectures such as the EPI project, RISC-V Monte Cimone cluster, Exascale Co-development for scientific applications in projects like Space and Max, and RISC-V demostrators for space and industrial use cases like TRISTAN and ISOLDE projects.
Link:
EPI https://www.european-processor-initiative.eu/
Monte Cimone https://arxiv.org/abs/2205.03725
Space https://www.space-coe.eu/
Max https://www.max-centre.eu/
TRISTAN https://tristan-project.eu/
ISOLDE https://www.isolde-project.eu/
Bilal Zafar
Co-Founder & CEO
10xEngineers
Biography:
Bilal Zafar is the co-founder & CEO of 10xEngineers, a design & verification services company focused on RISC-V.
10xEngineers has been an active contributor to the RISC-V ecosystem since its inception. Our cloud-based RISC-V software development and continuous integration (CI) service, Cloud-V, is helping accelerate software porting to RISC-V. Cloud-V is also the first RISC-V Lab Partner, offering software CI service free of charge to open-source communities. Today, projects like LLAMA.cpp run their RISC-V CI using Cloud-V. 10xEngineers is a RISC-V Development Partner, contributing to the RISC-V Architecture Tests and SAIL model development. We are now one of the maintainers of the arch-tech repositories. We have also been contributing to open-source RISC-V cores, especially the CVA6 family of cores, maintained by the OpenHW Group.
10xEngineers has hosted multiple RISC-V Hackathons and workshops to help grow the community at the grass-roots level across the globe. Bilal also teaches (part-time) to inspire students to join the semiconductor industry.
Before founding 10xEngineers, Bilal was a Principal Engineer/Manager at Qualcomm. He holds a Ph.D. in Computer Engineering from the University of Southern California, Los Angeles.
Nomination Comments:
I’ve been part of the RISC-V community since 2019 and have seen this community grow and mature very rapidly over the past five years. As a community, we have significant challenges ahead including compliance and certification, extending software support for RISC-V, and maintaining a single, global and open standard. These challenges can only be overcome through genuine collaboration between RISC-V International members and only a strong, diverse and vibrant board can facilitate this collaboration.
It is to help create such a board, that I wish to join the RISC-V International Board as a representative of the Strategic Members from all over the world. Our experience working on Architecture Compatibility Tests will also be useful as the board considers steps towards RISC-V Certification.
Art Swift
President and CEO
Esperanto Technologies, Inc.
Biography:
Art Swift is the President and CEO of Esperanto Technologies, a leading developer of high-performance, energy-efficient computing solutions based on the RISC-V instruction set architecture. He brings over 30 years of executive experience in the technology and microprocessor industry to Esperanto.
Art has held executive roles at prominent technology companies, including CEO at low-power processor maker Transmeta, and executive positions at MIPS, Digital Equipment’s Alpha processor group, and Sun Microsystems.
He has been deeply involved in advancing RISC-V, previously serving as Vice Chair of the RISC-V Foundation’s Marketing Committee. Art‘s extensive industry experience and vision have been instrumental in driving Esperanto’s innovations in massively parallel, energy-efficient RISC-V computing for Generative AI, High Performance Computing and other demanding workloads.
Art serves on the Board of Directors and Finance Committee of the Foothill-DeAnza Foundation, supporting STEM education. He also serves in advisory roles at the Science Learning Institute of Foothill College and cybersecurity firm CUPP Computing. He also held the role of President and served on the board of the prpl Foundation, an open-source non-profit focused on enabling security and interoperability for embedded devices and the Internet of Things.
Art Swift‘s extensive leadership experience across disruptive processor technologies, combined with his active involvement in the RISC-V ecosystem and advocacy for open standards and STEM education, position him as a compelling candidate for the RISC-V Foundation’s Board of Directors.
Nominees: Representative for Community Organization Members (1 seat)
Frank Gurkaynak
Senior Scientist
ETH Zurich
Biography:
Frank has received his B.Sc. and M.Sc. from the Istanbul Technical University, and his Ph.D degree from ETH Zurich. He is a senior scientist in the group of Luca Benini and is the director of the Microelectronics Design Center at ETH Zurich. He has been part of the PULP platform project since its beginning in 2013 and has been actively involved in RISC-V and open source activities.
Nomination Comments:
I have been actively involved in the RISC-V journey from quite an early time and will represent the view point of academic institutions if elected.
Fernando Idalirio Leite
Manager
Eldorado Research Institute
Biography:
I am responsible for IC Design team (Digital, Analog and MEMS) and for the Advanced Packaging Laboratory at Eldorado Research Institute in Brazil.
As Manager my activities are keep my technical Leaders with good capabilities (technical and soft skills) to assume and maintain projects in Digital, Analog and Advanced Heterogeneous Packaging. Focusing also, on strategic actions and to maintain continuous improvement, I have been providing continuous improvements for technical leaders and teams bringing specialized technical and training/coaching process to improve my department area to a new level, focusing on People, processes and technology.
My mission as Semiconductor manager is to provide knowledge and technology for our technological environment companies, I have been working on bringing new business and technology opportunities for companies in many areas like Memories, RISC-V Processors, photonics, MEMS, FPGA design, RTL design, verification design, testability, Physical Implementation and IC Design Architectural requirements and specifications. On the other hand, I am continuously improving connection with universities and other research institutes, here in Brazil and outside.
In addition to maintaining projects synchronized with cutting-edge global technologies, I have also maintain contact with general coordinators of technologies in digital transformation and semiconductors members of the Brazilian Ministry of Science and Technology, in order to meet national demands for new technologies for the Eldorado Research Institute.
I have experience with many semicondutors projects and services (see more detais in the attached curriculum), but the main project that motivates myself for this opportunity is the
“RISC-V Matrix Processing Unit (MPU) for HPC (High Performance Computing) Project”, that I am managing here at Eldorado Research Institute, this project consists in a development of software models for functional simulation, cycle-accurate simulation, and RTL model of a module for Matrix Processing Unit (MPU) that can later be integrated into a RISC-V platform. This will allow the country to begin technological acquisition in this area, and can later build a node for HPC/AI clusters. Throughout the project, it is expected that R&D activity and training of designers in technologies for RISC-V will be increased. This project will be carried out in partnership with the UNICAMP University and Barcelona Supercomputing Center (BSC) in Spain.
As Manager my activities are keep my technical Leaders with good capabilities (technical and soft skills) to assume and maintain projects in Digital, Analog and Advanced Heterogeneous Packaging. Focusing also, on strategic actions and to maintain continuous improvement, I have been providing continuous improvements for technical leaders and teams bringing specialized technical and training/coaching process to improve my department area to a new level, focusing on People, processes and technology.
My mission as Semiconductor manager is to provide knowledge and technology for our technological environment companies, I have been working on bringing new business and technology opportunities for companies in many areas like Memories, RISC-V Processors, photonics, MEMS, FPGA design, RTL design, verification design, testability, Physical Implementation and IC Design Architectural requirements and specifications. On the other hand, I am continuously improving connection with universities and other research institutes, here in Brazil and outside.
In addition to maintaining projects synchronized with cutting-edge global technologies, I have also maintain contact with general coordinators of technologies in digital transformation and semiconductors members of the Brazilian Ministry of Science and Technology, in order to meet national demands for new technologies for the Eldorado Research Institute.
I have experience with many semicondutors projects and services (see more detais in the attached curriculum), but the main project that motivates myself for this opportunity is the
“RISC-V Matrix Processing Unit (MPU) for HPC (High Performance Computing) Project”, that I am managing here at Eldorado Research Institute, this project consists in a development of software models for functional simulation, cycle-accurate simulation, and RTL model of a module for Matrix Processing Unit (MPU) that can later be integrated into a RISC-V platform. This will allow the country to begin technological acquisition in this area, and can later build a node for HPC/AI clusters. Throughout the project, it is expected that R&D activity and training of designers in technologies for RISC-V will be increased. This project will be carried out in partnership with the UNICAMP University and Barcelona Supercomputing Center (BSC) in Spain.
Nomination Comments:
I have been organizing and providing support for my Institute and mainly for aligment with national Semiconductors area roadmap. Brazil is already a Premium Member of the RISC-V association and I have been very involved with all main companies that are really interested to develop and contribute with RISC-V Community.
Amanda Brock
CEO
OpenUK
Biography:
Amanda is CEO of OpenUK, having spent 25 years as a lawyer, 15 of those at GC level. Having joined Canonical in 2008 as its first GC, she has 16 years of experience as part of the open source movement.
She is the editor of the book Open Source Law, Policy and Practice which includes a chapter on open hardware and the mandarin translation of which will be published in 2024. She has sat on board for over 20 years with both statutory and advisory board experience across open source including the 2012 drafting committee that set up Open Stack,the OSI Board and KDE Advisory Board. She is a Distinguished Fellow of the Rust Foundation.
She is the editor of the book Open Source Law, Policy and Practice which includes a chapter on open hardware and the mandarin translation of which will be published in 2024. She has sat on board for over 20 years with both statutory and advisory board experience across open source including the 2012 drafting committee that set up Open Stack,the OSI Board and KDE Advisory Board. She is a Distinguished Fellow of the Rust Foundation.
Amanda is listed in the Computer Weekly Most Influential UK Tech & Computing IT Leaders 100.
Amanda is a frequent writer for the tech press and international keynote speaker.
OpenUK is the unique industry organisation for the business of open technology including open hardware. It convenes the global open hardware community at its annual State of Open Con in London which now in its third through its open hardware track and recognises the UK open hardware community in its Annual Awards’ hardware category.
OpenUK convenes the open source communities to give them a cohesive voice in law and policy and to develop skills and learning. It undertakes research and reporting.
Nomination Comments:
The UK is evolving an increasing interest in open hardware. As a long term member of RISCV OpenUK is investigating a deeper partnership and to convene the relevant conversations across the open hardware communities to enhance UK leadership and global collaboration on open hardware.
Nominees: Representative for Community Individual Members (1 seat)
Tiejun Chen
Individual Member
Senior Technical Lead
Tiejun Chen
Senior Technical Lead
Biography:
Tiejun Chen is a Sr. technical leader. He’s been working for more than 20 years at several tech companies such as VMware, Intel, Wind River Systems and so on, involved in a lot of things from cloud to edge, form those low-level technologies such as hardware, OS, virtualization to cloud native, edge computing, even ML/AI, etc. He was ever a strategic Representative of RISC-V International TSC 2023, and now one of RISC-V ambassadors under RISC-V International.
He made many presentations at open source events such as AI.Dev 2023, kubecon China 2021, Kube Edge day Europe 2022, LC3 China 2017 & 2018, OSS China 2019, OSS North America 2017 & 2018, OSS & ELC Europe 2017 & 2018 & 2019, ELC & OpenIoT 2018, OSLS 2019, LF Edge mini-summit Europe 2019 and so on.
Specifically, he also was invited to share his explorations on RISC-V in RISC-V Summit 2019, 2022 and 2023. He would like to put all of what he’s doing or exploring in different areas of software development to RISC-V to help accelerate the adoption of RISC-V.
Comments on why I want to be on the RISC-V Board of Directors:
RISC-V is gaining momentum. Actually, over the past few years it has already got noticed from communities of embedded system, IoT, and even datacenter from on-prem to cloud. Many RISC-V processors and hardware platforms have been introduced. Indeed, in the meantime, the communities have started building up software ecosystems for RISC-V and really made good progress, however we should step forward with robust full stack software development ecosystems, not only tools, low-level runtimes, OS, etc. We should empower RISC-V’s widespread integration with software frameworks and platform from cloud to edge.
So, I think we need to come near to both the individual contributors, companies and investors involved in the RISC-V ecosystem by working closely with the communities under RISC-V international.
I’d like to take this opportunity to build RISC-V community as follows –
- As a community, we should be able to identify and prioritize potential software development. It should have a clear plan step by step with our guidance and support.
- We’d better focus on impactful near-term co-innovation through better alignment and collaboration with companies, vendors, and individual contributors.
- We should walk towards a new era of edge computing with Open Software on Open Hardware – RISC-V. This is something I tried to prompt somewhere already. Edge computing is set to experience substantial growth. Especially, LF Edge, an initiative hosted by the Linux Foundation, aims to create an open, interoperable software framework for edge computing. This platform is designed to operate independently of hardware, silicon, cloud, or even the operating system. In parallel, open-source hardware platforms are gaining traction within the realms of IoT and embedded systems, propelling the expansion of edge computing. This convergence of open software and RISC-V has the potential to usher in a new era of edge computing – Open Software on Open Hardware. While these fusion promises to facilitate the rapid adoption of edge computing, it also presents new opportunities within RISC-V integration with LF Edge.
- With the evolution of remarkable AI LLM, many new AI hardware accelerators including RISC-V based accelerators have been introduced. We should explore how to fit RISC-V into those ML frameworks and graph compilers. In addition, there are some new potential open source activities we should take a closer look at and get involved as soon as possible. Like UXL, https://uxlfoundation.org/, tries to build a multi-architecture multi-vendor software ecosystem for all accelerators and unify the heterogeneous compute ecosystem around open standards. There is no doubt RISC-V should be there.
- As we see some powerful RISC-V processors were launched recently to embrace datacenters. RISC-V has such a basic cloud native runtime supported. We need to guide the community to play forward to it by constructing end to edge cloud native platforms and frameworks on RISC-V.
There are a lot waiting for us around RISC-V. I’m eager to help accelerate the adoption of RISC-V as a Community Individual Member Representative.
Paul Sherman
Electrical Engineer
Individual Member
Biography:
see my github: psherman42 especially repo “riscv easy as pi”
https://github.com/psherman42/riscv-easy-as-pi
| Nomination Comments: |
I’e been at this awhile, since mid 1970s growin up with 6502 as purely an elementary hobbyist;and also am perhaps the only ddmocratic socialist in all of RIS -V International who has experience organizing others equally and fairly. I think I’d make a dynamite member of the Board, who everyone else would like, too.
Ishfaque Ahmed Khanzada
ICT Expert University of Karachi
Individual Member
Biography:
Engr Ishfaque Khanzada, an esteemed ICT Expert and Consultant at the University of Karachi (UoK), Pakistan, has dedicated over 14 years to the advancement of ICT infrastructure and autonomous systems development. With a robust background in computer engineering, Ishfaque holds a Master of Engineering degree, which has propelled him to the forefront of ICT innovations and deployments across Pakistan.
Throughout his career, Ishfaque has been instrumental in the successful execution of numerous multi-million dollar projects, both within the governmental and private sectors. His expertise in ICT infrastructure development has not only enhanced the technological landscape of various organizations but has also contributed significantly to the nation’s IT growth and modernization.
As a dedicated IEEE volunteer for over a decade, Ishfaque’s commitment to the field of IT is reflected in his numerous publications and presentations, where he has shared his knowledge and insights on ICT advancements. His contributions to the academic and professional community have been invaluable, earning him recognition and respect among his peers.
In addition to his professional achievements, Ishfaque is actively involved in community service, utilizing his skills and knowledge to benefit society. His unique and sharp intellect, combined with his unwavering dedication, makes him an exemplary candidate for any prestigious recognition.
Ishfaque Khanzada is not just a leader in ICT;he embodies the spirit of innovation, service, and excellence. His remarkable contributions and steadfast commitment to the field make him a deserving nominee who can undoubtedly excel and continue to drive significant advancements in RISC-V Community.
Throughout his career, Ishfaque has been instrumental in the successful execution of numerous multi-million dollar projects, both within the governmental and private sectors. His expertise in ICT infrastructure development has not only enhanced the technological landscape of various organizations but has also contributed significantly to the nation’s IT growth and modernization.
As a dedicated IEEE volunteer for over a decade, Ishfaque’s commitment to the field of IT is reflected in his numerous publications and presentations, where he has shared his knowledge and insights on ICT advancements. His contributions to the academic and professional community have been invaluable, earning him recognition and respect among his peers.
In addition to his professional achievements, Ishfaque is actively involved in community service, utilizing his skills and knowledge to benefit society. His unique and sharp intellect, combined with his unwavering dedication, makes him an exemplary candidate for any prestigious recognition.
Ishfaque Khanzada is not just a leader in ICT;he embodies the spirit of innovation, service, and excellence. His remarkable contributions and steadfast commitment to the field make him a deserving nominee who can undoubtedly excel and continue to drive significant advancements in RISC-V Community.
Nomination Comments:
I am honored to nominate myself as Engr. Ishfaque Khanzada for this prestigious recognition. Engr. Khanzada, an esteemed Information and Communication Technology Expert, has significantly advanced the Systems and Network Infrastructure, showcasing his exceptional leadership and technical skills, which can eventually flourish the community of RISC-V as a good resource.
Carl Perry
Operations, Development, and Community Engagement
Individual Member
Biography:
Carl is an Operations Developer by trade, and has always had a passion for learning and educating about computing in general. He runs the Austin RISC-V Group with a monthly informational meeting and a monthly hack-a-thon. He’s also a RISC-V Advocate and has a lot of experience with building communities and ecosystems around new architectures due to his time working on the Works on Arm program. He’s been working in the IT industry for over 25 years, and spent a lot of that time working to make the user experience better for everyone.
Nomination Comments:
I’ve been very active in various RISC-V groups specifically around the Advocates, Marketing, Events, Profiles, and most importantly Documentation. I strongly believe the most important part of being involved with RISC-V International is communication. We have a lot of sub-groups, and I don’t mean that in a negative way: hardware focused groups, software focused groups, and then even more deeply specific groups beyond that. But we don’t seem to have a lot of communication between those groups, or the community at large. I don’t claim to be an expert in all of these groups, but I do think it’s important to have a a lot of communication between them. It’s also important to have a dialog with the community at large. It’s easy to be in the echo-chamber, sometimes too easy. But it’s also important to reach beyond that and talk to users, understand what they need, and bring that back to the inner circles. From my perspective, RISC-V is on the fast track to follow the same path Arm tried to forge. A lot of that is good news! But there are are also a lot of lessons that are being overlooked. At the end of the day RISC-V International only produces an Open Standard, but it’s also an opportunity to have a greater discussion to make that Open Standard more useful for everyone and not just be relegated to an industry niche. We’re on the precipice of becoming something greater for everyone, it’s just a matter of communicating and I would be honored to try and bring that vision to the Board of Directors.
Abhishek Kumar
Individual Member
Embedded Systems Engineering
Abhishek Kumar
Embedded Systems Engineering
Biography:
As an Embedded Systems professional, I specialize in the design, development, and implementation of software and hardware systems that are integrated into products, devices, and machines. I have extensive experience in programming microcontrollers, designing printed circuit boards, and developing firmware to meet the requirements of various embedded applications. I have a deep understanding of computer architecture, real-time operating systems, and networking protocols that enable me to work effectively in a team and deliver robust solutions. My passion for technology, coupled with strong problem-solving skills, makes me a valuable asset to any organization looking to develop innovative embedded systems.
Comments on why I want to be on the RISC-V Board of Directors:
Abhishek Kumar’s biography reflects a seasoned professional deeply immersed in the world of embedded systems. His expertise spans both software and hardware realms, emphasizing his ability to navigate the intricacies of designing and implementing integrated systems. With a focus on microcontroller programming, PCB design, and firmware development, Abhishek showcases a comprehensive skill set crucial for crafting tailored solutions across various embedded applications.
His adeptness in computer architecture, real-time operating systems, and networking protocols underscores his versatility and readiness to tackle multifaceted challenges. Notably, Abhishek’s collaborative spirit shines through as he highlights his effectiveness within team settings, suggesting a commitment to collective success.
Moreover, his passion for technology and adept problem-solving capabilities further solidify his standing as a valuable contributor poised to drive innovation within any organization. Overall, Abhishek Kumar’s biography exudes confidence, competence, and a genuine enthusiasm for pushing the boundaries of embedded systems development