Membership Representative to the Board: 2024 Election

I am a Technical Fellow at Microchip’s FPGA BU, where I am responsible for defining its roadmap for low power, secure, reliable FPGAs and SoC FPGAs. I joined Actel (now part of Microchip) in 1987 and have held roles in process engineering and product engineering before assuming my current role in 2003. I am a co-inventor on 35 U.S. patents. In my role, I have consistently defined first of its kind products, the most recent example being PolarFireSoC, the first RISC-V based SoC FPGA. Prior to joining Actel, I worked at LSI Logic. I have a Bachelor of Science in chemical engineering from Cornell.

To the RISC-V Board of Directors,

I’d like to congratulate Ken and Jefro on their election.  There are few who can match their service to and impact on RISC-V.

Those few include both Philipp and Roger.  No matter, the outcome of this vote, the RISC-V Board will be in good shape.

I’m happy with my original nomination statement (below) but I thought I’d take the time to provide some more context and make a more personal appeal.

Let’s start with the personal appeal.  The reason you want me is that I’m different, in a lot of ways, most of them good.  I’ll try to highlight two of those which  I believe many of you can personally vouch for.

1. I have vision and, more than that, I have a track record of making vision a reality.  I’ll touch on an example later when I discuss commercialization.
2. I’m collaborative.  Collaboration includes helping everyone find their voice and being a trusted arbiter known for considering all sides.  Members have come to me to help resolve disputes with other members.  I reached out to new board members who joined just as we entered Covid and helped them understand the dynamics of board meetings.   While I certainly represent the ‘old guard’ on our board, I have embraced and supported the skills and priorities of the newer members who are helping us evolve to the next level.

Regarding commercial impact, I could make a long list of RISC-V firsts on the road to commercialization and adoption that Microchip can claim.   I can point out that Microchip’s exhibitor spend on RISC-V Events has been roughly $500k in just the last 3 years.

I would like to focus on HPSC … High Performance Space Computer ( https://www.microchip.com/en-us/products/microprocessors/64-bit-mpus/pic64-hpsc ) .   It is an SoC, designed and produced by Microchip, comprising an octal SiFive X280 vector processor.  When I first heard of RISC-V in 2015, I thought immediately of its potential in the space market and I’ve been pulling on the space thread since day one.  You’ll find a space theme woven into most of my talks.

The first RISC-V commercial IP purchase (and first time RISC-V beat Arm) was for a Microchip FPGA implementation for a satellite payload.  In addition to NASA, the European space market has selected RISC-V for future space processors.

I am positive that I have had a significant role in RISC-V capture of the space market.  My membership on the board was a big help.  I believe my continued participation on the board will enhance the success of RISC-V and the success of HPSC in the space market and in adjacent areas such as safety critical, vector processing, AI, and government affairs.

Finally, you may think that that the space market, while cool, is relatively minor.  I play the long game and I have believed that this market will become significant.   There is a lot of venture capital going toward the space market and projects such as lunar data centers are being funded.  RISC-V is already on the space station running Ubuntu and will be landing on the moon at the end of this year in support of such a venture.

Thank you for your consideration in this upcoming vote.

Ted

I have been a RISC-V leader and evangelist and have served on the Board of Directors of RISC-V International since its inception in 2016. I am currently serving my second term as Secretary.

I am proud of my leadership contributions to RISC-V International and to RISC-V in general which include:

As a board member,

– I have been very accessible and have relationships with members across the globe and with all classes of members including adopters, solution providers, academics and influencers.

– I am thought of as one who relates well with new board members, listens to them and helps them promote new perspectives they bring.

– I have played key leadership roles in all phases of our growth starting with evangelization, then execution and now commercialization.

My role as an adopter of RISC-V has made a significant commercial impact.

– The first RISC-V ever shipped in a product is believed to be an implementation in a Microchip FPGA.

– PolarFireSOC FPGA is among the first implementations of RISC-V in commercial silicon.

– Microchip is now building NASA’s High Performance Space Computer (HPSC) which is centered around RISC-V processors with vector extensions.

A key next phase challenge for RISC-V that I can impact during the next term is continued adoption of RISC-V in vertical segments. RISC-V’s success in the space market is transferrable to many domains including AI and automotive.

I would be honored to be elected to continue to serve as your Board representative. Thank you.

Roger Espasa is the founder and CEO of SemiDynamics, an IP supplier of RISC-V
cores supporting the RISC-V vector extension, Tensor Unit extension and
Gazzillion(tm) misses, targeted at HPC and Machine Learning. In addition,
SemiDynamics architected and designed the Esperanto Technologies’ 1024+ core
machine-learning 7nm SoC. Prior to Semidynamics, Roger was at Broadcom working
on an ARMV8 wide out-of-order core (2014-2016). Previously, Roger worked at
Intel (2002-20014) developing a vector extension for the x86 ISA, initially
deployed in XeonPhi (Larrabee) which then became AVX-512. Roger also led the
texture sampling unit for Larrabee. Roger then worked on Knight’s Landing
(14nm) and led the core for Knights Hill (10nm). Between 1999 and 2001 Roger
worked for the Alpha Microprocessor Group on a vector extension to the Alpha
architecture known as Tarantula. Roger got his PhD from UPC in 1997, has
published over 40 peer-reviewed papers on Vector Architectures, Graphics/3D
Architecture, Binary translation and optimization, Branch Prediction, and
Media ISA Extensions and holds 9 patents with 41 international filings.

I would like to represent the Strategic Members at the Board to keep pushing for RISC-V adoption across geos and markets.