Seeking experienced SOC RTL/ Integration Lead/Manager to lead the Micro-architecture, Integration and RTL development of High-Performance Data Processing Unit Chiplets and Automotive Microcontrollers. The Candidate will be responsible for all aspects of the design including Schedule, Performance, Power, and Area.

Minimum Qualifications:

• Bachelors or Masters equivalent in Computer Science, Computer Engineering, Electrical Engineering or related fields.
• 10+ years of experience in RTL design or verification background.
• Knowledge of System Verilog, UVM, UPF and parametrized designs and configurable designs.
• Hands-on knowledge of high-performance microcontroller or Micro-processor architectures.
• Experience with major EDA tool vendor tools like Synopsys/Cadence/Tessent is desirable. Hands on knowledge of Synopsys Tools is preferable.
• In depth and hands on knowledge of bus architecture like AXI/AHB/equivalent protocols and various peripherals/CPU core integration.
• Excellent analytical and problem-solving skills, with great execution focus.
• Good leadership capabilities to lead a team of engineers and contractors to accomplish the organization goals.

Preferred Qualifications:

• Experience with designing RISC-V, ARM and/or MIPS CPU
• Understanding of low power micro-architecture techniques
• Experience using a scripting language such as Perl or Python
• Experience with ISO2626/FuSa

Roles and Responsibilities:

• Lead and build a team of SOC RTL/Integration engineers to develop next generation high performance Data Processing Chiplets/Automotive microcontrollers.
• Hands-on development of micro-architecture and key design specifications and modules.
• Setup development flows and automation methodology for improved development efficiency.
• Create design specifications, functional block diagrams, code development and documentation for the SOC IP blocks and integration.
• Independently code, debug and lead Verilog RTL development for high performance designs and mentor the team.
• Synthesis, Equivalence Checks, Clock Domain Crossing (CDC), Area/Power optimization, Linting, Static Timing analysis (STA).
• Contribute to Synthesis, Power reduction, timing convergence, floor plan efforts in collaboration with Physical Design Team.
• Collaborate with leadership team to hire engineers and contractors required to execute the project in collaboration with the leadership team.

The base salary range across the U.S. for this role is between $145,000- $230,000. In addition, this role may be eligible for equity, and other discretionary bonuses. MIPS offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job-related factors, including location, skills, experience, and education.

Here’s what you can expect from us:
At MIPS, you’ll be a member of a fast-growing team of technologists that are creating the industry’s highest performance RISC-V processors.  Small teams that are part of a non-compartmentalized structure – you’ll be able to understand and have an impact on the bigger picture. A great deal of autonomy, with support from some of the industry’s most experienced CPU engineers. An unlimited growth path – with the right skills, you can decide where you want to expand and grow in your role at MIPS. The opportunity to learn a great deal about the blossoming RISC-V architecture in cutting edge applications with industry leading customers.

At MIPS we provide meaningful benefits programs and products to our associates and their families. MIPS offers a competitive benefits package that includes medical, dental, vision, retirement savings, and paid leave!

More about us:
MIPS is well-known as a microprocessor pioneer, having led the way in RISC-based computing to enable faster and more power efficient semiconductors for a wide range of applications from consumer electronics to networking and communications. More than 30 years after the introduction of the original MIPS RISC architecture, MIPS processors have shipped into billions of consumer and enterprise products.

Today, MIPS is once again leading a RISC revolution as we build on our deep roots to accelerate the RISC-V architecture for high-performance applications. We are focused on delivering our first RISC-V products: the MIPS eVocore processors, which provide a new level of scalability for high-performance heterogeneous computing. Because of our RISC heritage, deep engineering expertise, and proven technologies, MIPS can accelerate development and deployment of RISC-V based solutions.