We have a position in our RTL team and we’re looking for Senior RTL Engineer with either a strong RTL or a strong architecture/microarchitecture background interested in working in several areas of a RISC-V design for an advanced technology node. In particular, areas of focus will be the processor pipeline, d-cache, i-cache, the l2-pipeline and a custom memory controller. Expertise in PCS and FEC is required. We believe in very “vertical” engineers that fully understand the problem to be solved and can take it down to RTL level.

Requirements